我尝试使用查找表将二进制的verilog代码写入RNS转换器。它的概念类似于例如我输入a = 10100100，因此sum8 = 100（最后3位数），sum7 = 2 ^ 2 + 2 ^ 5 + 2 ^ 7，sum5 = 2 ^ 2 + 2 ^ 5 + 2 ^ 7，sum3 = 2 ^ 2 + 2 ^ 5 + 2 ^ 7 .....我们从查找表中找到这些2 ^值。在我的代码中我直接将这两个值分配为（mod3，mod5，mod7）值，但我没有得到sum5，sum3，sum7的正确结果（我得到未定义的输出）....我的代码如下。 有没有其他优化的编写代码的方法？
module spram(,clk,a,dout,mod3,mod5,mod7,bin,sum3,sum5,sum7,sum8
);
input wire clk;
input [7:0] a;
output [4:0]sum3;
output [4:0]sum5;
output [4:0]sum7;
output reg [2:0]sum8;
reg [2:0]s30,s31,s32,s33,s34,s35,s36,s37,s38,s39,s50,s51,s52,s53,s54,s55,s56,s57,s58,s59,s70,s71,s72,s73,s74,s75,s76,s77,s78,s79;
parameter ADD_WIDTH = 4;
parameter DATA_WIDTH = 24;
reg [ADD_WIDTH-1:0] addr;
output reg [DATA_WIDTH-1:0]dout;
output reg [2:0]mod3;
output reg [2:0]mod5;
output reg[2:0]mod7;
output reg [8:0]bin;
always@(addr)
begin
case(addr)
4'b0000:
begin
dout<=24'b 000000001001001001;
mod3<= 3'b 001;
mod5<= 3'b 010;
mod7<= 3'b 001;
bin<= 9'b 000000001 ;
s30<=mod3;
s70<=mod7;
s50<=mod5;
//sum8<= a[2:0];
end
4'b0001:
begin
dout<=24'b 000000010010010010;
mod3<=3'b 010;
mod5<=3'b 010;
mod7<=3'b 010;
bin<=9'b 000000010;
s31<=mod3;
s71<= mod7;
s51<= mod5;
end
4'b0010:
begin
dout<=24'b 000000100100100001;
mod3<=3'b 001;
mod5<=3'b 100;
mod7<=3'b 100;
bin<=9'b 000000100;
s32<=mod3;
s72<= mod7;
s52<= mod5;
end
4'b0011:
begin
dout<=24'b 000001000001011010;
mod3<=3'b 010;
mod5<=3'b 011;
mod7<=3'b 001;
bin<=9'b 00000100;
s33<=mod3;
s73<= mod7;
s53<= mod5;
end
4'b0100:
begin
dout<=24'b 000010000010001001;
mod3<=3'b 001;
mod5<=3'b 001;
mod7<=3'b 010;
bin<=9'b 000010000;
s34<=mod3;
s74<=mod7;
s54<=mod5;
end
4'b0101:
begin
dout<=24'b 000100000100010010;
mod3<=3'b 010;
mod5<=3'b 010;
mod7<=3'b 100;
bin<=9'b 000100000;
s35<=mod3;
s75<= mod7;
s55<= mod5;
end
4'b0110:
begin
dout<=24'b 000100000100010010;
mod3<=3'b 010;
mod5<=3'b 010;
mod7<=3'b 100;
bin<=9'b 000100000;
s36<=mod3;
s76<=mod7;
s56<= mod5;
end
4'b0111:
begin
dout<=24'b 001000000010011010;
mod3<=3'b 010;
mod5<=3'b 011;
mod7<=3'b 010;
bin<=9'b 001000000;
s37<=mod3;
s77<= mod7;
s57<= mod5;
end
4'b1000:
begin
dout<=24'b 010000000100001001;
mod3<=3'b 001;
mod5<=3'b 001;
mod7<=3'b 100;
bin<= 9'b 010000000;
s38<=mod3;
s78<= mod7;
s58<= mod5;
end
4'b1001:
begin
dout<=24'b 100000000001010010;
mod3<=3'b 010;
mod5<=3'b 010;
mod7<=3'b 001;
bin<=9'b 100000000;
s39<=mod3;
s79<= mod7;
s59<= mod5;
end
default:
begin
dout<=24'd0;
mod3<=3'b000;
mod5<=3'b000;
mod7<=3'b000;
bin<=9'd0;
end
endcase
end
assign sum5= s50+s51+s52+s53+s54+s56+s57+s58+s59;
assign sum3= s30+s31+s32+s33+s34+s36+s37+s38+s39;
assign sum7= s70+s71+s72+s73+s74+s76+s77+s78+s79;
always@(posedge clk)
begin
sum8<= a[2:0];
if (a[0]==1)
addr<=4'b0000;
else if (a[1]==1)
addr<=4'b0001;
else if (a[2]==1)
addr<=4'b0010;
else if (a[3]==1)
addr<= 4'b0011;
else if (a[4]==1)
addr<=4'b0100;
else if (a[5]==1)
addr<= 4'b0110;
else if (a[6]==1)
addr<= 4'b0111;
else if (a[7]==1)
addr<= 4'b1000;
end
endmodule