所以我正在尝试在FPGA上实现I2C主设备，并且我得到以下错误。有人知道如何解决它们吗？ 谢谢！
警告：Xst：646 - 信号＆lt; thirdaddress＆gt;已分配但从未使用过。在优化过程中将修剪此未连接的信号。
警告：Xst：646 - 信号＆lt; secondaddress＆gt;已分配但从未使用过。在优化过程中将修剪此未连接的信号。
警告：Xst：646 - 信号＆lt; firstaddress＆gt;已分配但从未使用过。在优化过程中将修剪此未连接的信号。
警告：Xst：736 - 找到信号＆lt; Mtridata_sda＆gt;的1位锁存器。在第44行创建。锁存可以从不完整的case或if语句生成。我们不建议在FPGA / CPLD设计中使用锁存器，因为它们可能会导致时序问题。
警告：Xst：736 - 找到信号＆lt; Mtrien_sda＆gt;的1位锁存器在第44行创建。锁存可以从不完整的case或if语句生成。我们不建议在FPGA / CPLD设计中使用锁存器，因为它们可能会导致时序问题。
警告：Xst：737 - 找到信号＆lt; sendcount＆gt;的3位锁存器。锁存器可以从不完整的case或if语句生成。我们不建议在FPGA / CPLD设计中使用锁存器，因为它们可能会导致时序问题。
警告：Xst：1293 - FF / Latch＆lt; XLXI_9 / sendcount_2＆gt;块＆lt; top_level＆gt;中的常量值为0。在优化过程中将修整此FF / Latch。
警告：Xst：1293 - FF / Latch＆lt; XLXI_9 / sendcount_1＆gt;块＆lt; top_level＆gt;中的常量值为0。在优化过程中将修整此FF / Latch。
警告：Xst：1293 - FF / Latch＆lt; XLXI_9 / sendcount_0＆gt;块＆lt; top_level＆gt;中的常量值为0。在优化过程中将修整此FF / Latch。
警告：Xst：1896 - 由于其他FF / Latch修整，FF / Latch＆lt; XLXI_9 / current_state_FSM_FFd1＆gt;块＆lt; top_level＆gt;中的常量值为0。在优化过程中将修整此FF / Latch。
警告：Xst：1294 - Latch＆lt; XLXI_9 / Mtridata_sda＆gt;相当于块＆lt; top_level＆gt;中的电线。
警告：Xst：1294 - Latch＆lt; XLXI_9 / Mtrien_sda＆gt;相当于块＆lt; top_level＆gt;中的电线。
以下是代码：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity i2cmaster is
Port ( sda : inout STD_LOGIC;
scl : out STD_LOGIC;
sclclk : in STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC;
dataout : out STD_LOGIC_VECTOR (7 downto 0);
resettodivider : out STD_LOGIC);
end i2cmaster;
architecture Behavioral of i2cmaster is
type state_type is (startstate1, startstate2, sendaddress1, acknowlegde1, sendinternaladdress, acknowlegde2, startstate3, startstate4, sendaddress2, acknowlegde3, readdata, notacknowlegde, stopstate );
signal current_state : state_type;
signal next_state : state_type :=startstate1;
signal firstaddress: std_logic_vector(7 downto 0);
signal secondaddress: std_logic_vector(7 downto 0);
signal thirdaddress: std_logic_vector(7 downto 0);
signal sendcount: integer range 0 to 7 := 0;
signal temp : std_logic := '0';
signal tempdata : std_logic_vector(7 downto 0):="00000000";
begin
firstaddress<="10101010"; -- Slaveaddress + Writebit
secondaddress<="10101010"; -- Internal Address(first)
thirdaddress<="10101010"; -- Slaveaddress + Readbit
process(current_state, sda, sclclk, temp, sendcount, firstaddress, secondaddress, thirdaddress)
begin
case current_state is
------------------------
when startstate1 =>
temp<='0';
sendcount <=0;
resettodivider <='1';
sda<='1';
next_state <= startstate2;
------------------------
when startstate2 =>
temp<='0';
sendcount <=0;
resettodivider <='0';
sda<='0';
if sclclk = '0' then
next_state <= sendaddress1;
else
next_state <= startstate2;
end if;
------------------------
when sendaddress1 =>
resettodivider <='0';
if sendcount <= 7 then
if sclclk = '0' and temp='0' then
sda<=firstaddress(sendcount);
sendcount <= sendcount + 1;
temp<='1';
next_state<=sendaddress1;
elsif sclclk='1' then
temp<='0';
sendcount <=sendcount;
next_state<=sendaddress1;
else
temp<='0';
sda<='Z';
sendcount <= sendcount;
next_state<=sendaddress1;
end if;
else
temp<='0';
sendcount <= 0;
next_state<=acknowlegde1;
end if;
------------------------
when acknowlegde1 =>
temp<='0';
resettodivider <='0';
sendcount <=0;
if sclclk='1' then
if sda ='1' then
next_state<=startstate1;
else
next_state<=acknowlegde1;
end if;
else
next_state<=sendinternaladdress;
end if;
------------------------
when sendinternaladdress =>
resettodivider <='0';
if sendcount <= 7 then
if sclclk = '0' and temp='0' then
sda<=secondaddress(sendcount);
sendcount<= sendcount + 1;
temp<='1';
next_state<=sendinternaladdress;
elsif sclclk='1' then
temp<='0';
sendcount <=sendcount;
next_state<=sendinternaladdress;
else
temp<='0';
sendcount <= sendcount;
next_state<=sendinternaladdress;
sda<='Z';
end if;
else
temp<='0';
sendcount<= 0;
next_state<=acknowlegde2;
end if;
------------------------
when acknowlegde2 =>
sendcount <=0;
temp<='0';
resettodivider <='0';
if sclclk='1' then
if sda ='1' then
next_state<=startstate1;
else
next_state<=acknowlegde2;
end if;
else
next_state<=startstate3;
end if;
------------------------
when startstate3 =>
sendcount <=0;
temp<='0';
resettodivider <='1';
sda<='1';
next_state <= startstate4;
------------------------
when startstate4 =>
temp<='0';
resettodivider <='0';
sda<='0';
sendcount <=0;
if sclclk = '0' then
next_state <= sendaddress2;
else
next_state <= startstate4;
end if;
------------------------
when sendaddress2 =>
resettodivider <='0';
if sendcount <= 7 then
if sclclk = '0' and temp='0' then
sda<=thirdaddress(sendcount);
sendcount<= sendcount + 1;
temp<='1';
next_state<=sendaddress2;
elsif sclclk='1' then
sendcount<= sendcount;
temp<='0';
next_state<=sendaddress2;
else
sendcount<= sendcount;
temp<='0';
sda<='Z';
next_state<=sendaddress2;
end if;
else
temp<='0';
sendcount <=0;
next_state<=acknowlegde3;
end if;
------------------------
when acknowlegde3 =>
temp<='0';
sendcount<=0;
resettodivider <='0';
if sclclk='1' then
if sda ='1' then
next_state<=startstate1;
else
next_state<=acknowlegde3;
end if;
else
next_state<=readdata;
end if;
------------------------
when readdata =>
resettodivider <='0';
if sendcount <= 7 then
if sclclk = '0' and temp='0' then
tempdata(sendcount)<=sda;
tempdata<=tempdata;
sendcount<= sendcount + 1;
temp<='1';
next_state<=readdata;
elsif sclclk='1' then
tempdata(sendcount)<='0';
temp<='0';
sendcount <= sendcount;
next_state<=readdata;
else
temp<='0';
tempdata(sendcount)<='0';
sendcount <= sendcount;
next_state<=readdata;
end if;
else
temp<='0';
tempdata(sendcount)<='0';
sendcount <= 0;
next_state<=notacknowlegde;
end if;
------------------------
when notacknowlegde =>
sendcount<=0;
temp<='0';
resettodivider <='0';
if sclclk='0' then
next_state<=stopstate;
sda<='Z';
else
sda<='1';
next_state<=notacknowlegde;
end if;
------------------------
when stopstate =>
sendcount<=0;
temp<='0';
sda<='0';
resettodivider <='1';
next_state<=startstate1;
------------------------
when others =>
sendcount<=0;
temp<='0';
resettodivider <='0';
next_state<=startstate1;
sda<='Z';
scl<='Z';
end case;
end process;
-------
process(clk, reset)
begin
if (reset='1') then
current_state <= startstate1;
elsif rising_edge(clk) then
current_state <= next_state;
end if;
end process;
-------
scl<=sclclk;
dataout<= tempdata;
end Behavioral;
答案 0 :(得分：2)
抱怨死/未使用的代码
WARNING:Xst:646
Signal <thirdaddress> is assigned but never used.
Signal <secondaddress> is assigned but never used.
Signal <firstaddress> is assigned but never used.
这意味着您的设计中未使用这三个信号。如果您以后不打算使用它们，可以将其删除 - ＆gt;死代码。
关于锁存的警告 - ＆gt;糟糕的设计
WARNING:Xst:736
Found 1-bit latch for signal <Mtridata_sda> created at line 44.
Found 1-bit latch for signal <Mtrien_sda> created at line 44.
Found 3-bit latch for signal <sendcount>.
Latches may be generated from incomplete case or if statements.
We do not recommend the use of latches in FPGA/CPLD designs, as
they may lead to timing problems.
您的状态转换过程不会为每个输入组合分配每个输出信号。这可以通过扩展您的其他案例或通常在案例陈述之前引入默认分配来解决。
关于寄存器的警告，这些寄存器不会改变值=＆gt;持续内容
WARNING:Xst:1293
FF/Latch <XLXI_9/sendcount_2> has a constant value of 0 in block <top_level>.
FF/Latch <XLXI_9/sendcount_1> has a constant value of 0 in block <top_level>.
FF/Latch <XLXI_9/sendcount_0> has a constant value of 0 in block <top_level>.
This FF/Latch will be trimmed during the optimization process.
您的计数器sendcount已被删除。这种故障主要是在以下情况下引起的：
- FSM挂起并且不会为计数器生成控制权
- 计数器保持重置
- 计数器没有获得任何增量/启用信号
未达到状态的警告
WARNING:Xst:1896
Due to other FF/Latch trimming, FF/Latch <XLXI_9/current_state_FSM_FFd1> has
a constant value of 0 in block <top_level>.
This FF/Latch will be trimmed during the optimization process.
这是传播信息。修整电路一端的寄存器，锁存器和逻辑可以进一步优化＆＃34; /在另一边修剪。
可以在综合报告中找到未达到的状态报告。搜索＆＃39;未到达＆＃39;。