Question

我正在为项目使用有限状态机，但是当我去模拟它时，当我将shift_button发送到'1'时，我得到一个迭代错误。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity LFSR_FSM is
    Port ( load_button : in  STD_LOGIC;
           input : in  STD_LOGIC_VECTOR (7 downto 0);
           key : inout  STD_LOGIC_VECTOR (7 downto 0);
           shift_button : in  STD_LOGIC;
              Clock : in STD_LOGIC);
end LFSR_FSM;
architecture Behavioral of LFSR_FSM is

type State_type is (Prime,Shift,Memory); 
signal Sreg, Snext: State_type; 
signal mem,shifted_output : STD_LOGIC_VECTOR (7 downto 0);
signal seven,six,five,four,three,two,one,zero : STD_LOGIC; 
begin
    process (Sreg,input,load_button,shift_button)
        begin 
        case Sreg is 
            when Memory => if shift_button = '1' then Snext <= Shift;
                               elsif load_button =  '1' then Snext <= Prime;
                                else Snext <= Memory; 
                           end if;  

            when Shift  => Snext <= Memory;


            when Prime => if load_button = '1' then Snext <= Prime;
                             else Snext <= Memory; 
                            end if;

            when others => Snext <= Memory; 
        end case;
end process; 
process (Clock)
    begin 
     if Clock'event and Clock = '1' then 
     Sreg <= Snext; 
     end if;
end process; 

--key <= output ;
with Sreg select 
key <= input when Prime,
       shifted_output when Shift,
         mem when others;
mem <= key;
shifted_output<=(zero,seven,six,five,four,three,two,one);
    seven <= mem(7); 
    six <= mem(6); 
    five <=  mem(0) xor mem(6);
    four <= mem(0) xor mem(5);
    three <= mem(0) xor mem(4);
    two <= mem(2);
    one <= mem(1);
    zero <= mem(0); 
end Behavioral;

这就是我在模拟结束时所拥有的 20 ns后load_button＆lt; ='1'，30 ns后'0'，40 ns后'1'，50 ns后'0';
在10 ns后输入＆lt; =“00110100”; 60 ns后shift_button＆lt; ='1'，70 ns后'0';

Answer 1

当FSM进入key -> mem -> (numbers) -> shifted_output -> key状态时，您有一个涉及Shift的组合循环。这导致您的模拟器迭代三角形循环，直到达到其极限。我建议通过将with-select移动到时钟进程来注册关键信号。如果使用VHDL-2008或将其转换为具有早期标准的案例陈述，它可以保持不变。

有人可以帮我找到我在循环VHDL卡住的地方

1 个答案: