Question

我的代码描述了用于控制交通信号灯的FSM。有四种状态，每种状态都有不同持续时间。

每当计数器等于1时，计数器需要再多一个时钟才能更改为下一个值。例如，在state1，计数器被编程为从4到1计数。每个值应该只需要一个时钟更改为下一个，当它发生时，状态将更改为下一个状态。但是当计数器等于1时，需要两个时钟来改变。

我的程序如下。计数器在always块的底部实现：

module HW3(times,A,B,clk,rst,iHand,iChang,s1);

input clk,rst;
output reg [2:0]A,B;
wire oclk;//new freq
reg [2:0] count1,count2,count3,count4;//count times
reg  [2:0]times;
reg temp;//control the switch 
parameter [2:0]state1=3'd0,state2=3'd1,state3=3'd2,state4=3'd3;

always@(posedge clk or negedge rst  )
    begin 


                if(!rst)
                    begin
                        s1<=state1;
                        A<=3'b0;
                        B<=3'b0;
                        count1<=3'd4;
                        count2<=3'd2;
                        count3<=3'd3;
                        count4<=3'd2;
                        temp<=1'b1;
                    end
                else
                    begin
                        if(temp==1)
                            begin
                                temp<=1'b0;
                                case(s1)
                                    state1:
                                        begin
                                            times<=count1;
                                            A<=3'b001;
                                            B<=3'b100;
                                            s1<=state2;
                                        end
                                    state2:
                                        begin
                                            times<=count2;
                                            A<=3'b010;
                                            B<=3'b100;
                                            s1<=state3;             
                                        end
                                    state3:
                                        begin
                                            times<=count3;
                                            A<=3'b100;
                                            B<=3'b001;
                                            s1<=state4;

                                        end
                                    state4:
                                        begin
                                            times<=count4;
                                            A<=3'b100;
                                            B<=3'b010;
                                            s1<=state1;
                                        end
                                    default:
                                        begin
                                            A<=3'b000;
                                            B<=3'b000;
                                        end
                                    endcase
                            end 
                        else
                            begin
                                if(times>1)
                                    times<=times-1;
                                else if(times==1)
                                    begin
                                        temp<=1'b1;//can't count averagely

                                    end
                            end
                    end

    end 
endmodule

Answer 1

Modify the code at the bottom of the always clock as:   

if(times>2)
 times<=times-1;
         else if(times==2)
                 begin
                         times=times-1;
                         temp<=1'b1;//can't count averagely

                      end

让时间计数到2，因为如果让它数到1，程序将再次输入if

在下一个时钟中阻塞，但不改变次数值，并使times = 1的值不变

再多一个时钟

伯爵很奇怪

1 个答案: