Question

我是VHDL的新人。我试图在下图中实现框图： enter image description here 实现Z ^ 1块（这只是一个延迟）的代码如下：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity DFF is 
    generic (N : INTEGER:=16);
    port( 
      D     : in  signed(N-1 downto 0);      -- Data input
      clk   : in std_logic;                  -- Clock input   
      reset : in std_logic;                  -- Reset input
      Q     : out signed(N-1 downto 0));     -- Data output
end DFF;

  architecture Behavioral of DFF is 
  begin
     DFF:process(clk)
     begin
         IF (clk'EVENT AND clk='1') THEN
             FOR i IN 0 TO N-1 LOOP
                 Q(i) <= reset AND D(i);      
             END LOOP;
         END IF;
     END process DFF;

  end Behavioral;

实现整个框图的代码如下：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity fir is
    generic (N : INTEGER:=16);
    port(   
        Clk         : in std_logic;              --clock signal    
        reset       : in std_logic;
        Xin         : in signed(N-1 downto 0);   --input signal
        Yout        : out signed(N-1 downto 0)   --filter output
    );
end fir;

architecture fir_struct of fir is

    component dff is  

        generic (N : INTEGER:=16);
        port(
            D           : in  signed(N-1 downto 0);
            clk         : in  std_logic;    
            reset       : in std_logic;
            Q           : out signed(N-1 downto 0));
   END component;   

signal y_delayed, add2_in1, add2_in2, y_temp : signed(N-1 downto 0) := (others => '0');  

-- add2_in1 is the first input of the adder (The input of the block diagram)
-- add2_in2 is the delayed output of the adder
-- y_temp is the output of the adder
-- y_delayed is the output of the delay operation

begin

    add2_in1 <= Xin;
    y_temp <= add2_in1 + add2_in2;   -- this line is giving me troubles

    DELAY1: dff port map(y_temp, Clk, reset, y_delayed);

    Yout <= y_temp;
    add2_in2 <= y_delayed;

end fir_struct;

我强调了让我烦恼的路线。我试图删除它并将DELAY1的第一个参数作为我的输入Xin（只是为了尝试它是否有效或问题是在另一行）并且它有效（当然它没有做我想要的，但是波形表现得和我一样。测试平台如下：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY iir_wav_tb IS
END iir_wav_tb;

ARCHITECTURE behavior OF iir_wav_tb IS                

    signal Clk          : std_logic := '0'; 
    signal reset        : std_logic := '1';
    signal Xin          : signed(15 downto 0) := (others => '0');
    signal Yout         : signed(15 downto 0) := (others => '0');
    constant Clk_period : time := 10 ns;     

begin   

   -- Instantiate the Unit Under Test (UUT)
   uut: entity work.fir PORT MAP (
       Clk => Clk, 
       reset => reset,
       Xin => Xin,
       Yout => Yout);

   -- Clock process definitions
   Clk_process :process
   begin
        Clk <= '0';
        wait for Clk_period/2;
        Clk <= '1';
        wait for Clk_period/2;  
   end process;

   -- Stimulus process
   stim_proc: process
   begin 
            Xin <= to_signed(1,16);
            wait for clk_period*1;

            Xin <= to_signed(23,16);    
            wait for clk_period*1;
    end process;
end

我获得的波形如下：

enter image description here

问题是当发生添加操作时，y_temp的值变为＆＃39;？＆＃39; （这个16位信号的分量都是＆＃39; X＆＃39;）。我认为这是一个无法实现的问题，因为直接通过辛而不添加任何东西都不会引发问题。有谁可以帮助我？

Answer 1

在开始使用代码之前，您需要记住VHDL是用于创建硬件而且它不是软件语言。因此，每个过程都由模拟器并行执行。只有变量才会立即执行。

其次，不要初始化不需要初始化的信号。

所以，我提出了这个改变：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity DFF is 
   generic (N : INTEGER:=16);
   port( 
      D     : in  signed(N-1 downto 0);      -- Data input
      clk   : in std_logic;                  -- Clock input   
      reset : in std_logic;                  -- Reset input
      Q     : out signed(N-1 downto 0))      -- Data output
   end DFF;

architecture Behavioral of DFF is 
begin
   DFF:process(clk,reset)
   begin
     IF (reset = '0') then
        Q <= (others => '0');
     elsif (clk'EVENT AND clk='1') THEN
        Q <= D;      
     END IF;
 END process DFF;

end Behavioral;

这样做，你在触发器内初始化add2_in2（它必须是从0开始的复位到1）。你不需要循环来分配每一位。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity fir is
    generic (N : INTEGER:=16);
    port(   
       Clk         : in std_logic;              --clock signal    
       reset       : in std_logic;
       Xin         : in signed(N-1 downto 0);   --input signal
       Yout        : out signed(N-1 downto 0)   --filter output
     );
end fir;

architecture fir_struct of fir is

component dff is  

    generic (N : INTEGER:=16);
    port(
        D           : in  signed(N-1 downto 0);
        clk         : in  std_logic;    
        reset       : in std_logic;
        Q           : out signed(N-1 downto 0));
END component;   

signal y_delayed, y_temp : signed(N-1 downto 0);

-- add2_in1 is the first input of the adder (The input of the block diagram)
-- add2_in2 is the delayed output of the adder
-- y_temp is the output of the adder
-- y_delayed is the output of the delay operation

begin

   y_temp <= Xin + y_delayed;

   DELAY1: dff port map(y_temp, Clk, reset, y_delayed);

   Yout <= y_temp;

end fir_struct;

我认为你的加法器会起作用。您需要更新您的测试平台：

signal reset        : std_logic;

process
begin
    reset <= '0';
    wait for 5 ns;
    reset <= '1';
    wait;
end process;

如果我忘记了什么，请问我。

VHDL - 在Signed之间添加操作

1 个答案: