Question

我是VHDL的新手。这里我有一个程序来计算两个数字的GCD。我有一堆案例和if语句。当我尝试模拟时，它给出了6个没有太多描述的错误

错误： 'U：\ GCD.dwv'错误0第41行：语法错误 'U：\ GCD.dwv'错误0第43行：语法错误

有趣的是它们每个被2行分开。因此它从第33行开始，并以相同的错误上升到43。它从“当S3 =＆gt;”开始在线。这是我的代码。谢谢！

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity GCD is
    port(clk, st : in std_logic; d1, d2 : in std_logic_vector(15 downto 0); dout : out std_logic_vector(15 downto 0); rdy : out std_logic);
end GCD;


architecture behav of GCD is
type state is (S0, S1, S2, S3, S4, S5, S6, S7);
signal new_state : state;
signal eq, It, eq1 : boolean;

begin
        --State Transition Process 
    process is
    variable curr_state : state := S0;
    begin

    if clk ='1' then
        case curr_state is
            when S0 =>
                if st='1' then curr_state := S1;
                end if;
            when S1 =>
                curr_state := S2;
            when S2 =>
                if eq then curr_state := S7;
                else if It then curr_state := S4;
                else if not(eq or It) then curr_state := S3;
                end if;
            when S3 =>
                curr_state := S4;
            when S4 =>
                curr_state := S5;
            when S5 =>
                if eq1 then curr_state := S7;
                else curr_state := S6;
                end if;
            when S6 =>
                curr_state := S1;
            when S7 =>
                if not(st) then curr_state := S0;
                end if;
        end case;
        new_state <= curr_state;
    end if;
    wait on clk;
end process;


-- Asserted Outputs Process:

process is

variable M, N, T, dout_val : std_logic_vector(15 downto 0);
variable rdy_val : std_logic;
variable eq_val, It_val, eq1_val : boolean;
begin

    rdy_val := '0';
    case new_state is
        when S0 =>
            M := d1; N := d2;
        when S1 =>
            eq_val := M=N; It_val := to_integer(M) < to_integer(N);
        when S2 =>
        when S3 =>
            M := T; M := N; N := T;
        when S4 =>
            eq1_val := to_integer(M) = 1;
        when S5 =>
        when S6 =>
            N := N - M; 
        when S7 =>
            rdy_val := '1'; dout_val := M; 
    end case;
    eq <= eq_val;
    It <= It_val;
    eq1 <= eq1_val;
    rdy <= rdy_val;
    dout <= dout_val;
    wait on new_state;
end process;


end behav;

Answer 1

而不是else if使用elsif。潜伏在那里可能会有更多错误。

use ieee.std_logic_unsigned.all;  -- because you use std_logic_arith

......国家过渡进程：

        when S7 =>
            if st = '0' then -- not (st) then 
                curr_state := S0;
            end if;

......输出流程：

        when S1 =>
            eq_val := M = N; 
            -- It_val := to_integer(M) < to_integer(N);
            It_val := M < N;

        when S4 =>
            -- eq1_val := to_integer(M) = 1;
            eq_val := conv_integer(M) = 1;

VHDL对分隔符有明确的要求，其余的是样式。由于缺乏一致的风格，您的代码需要仔细阅读。

其他读者无疑会建议使用包numeric_std，如果您使用的是VHDL -2008兼容工具，则包std_numeric_unsigned而不是Synopsys - 非标准使用包std_logic_arith和std_logic_unsigned。您尝试使用to_integer来自std_logic_unsigned。

Answer 2

我想举例说明我如何编写FSM。我希望它对你的目的有用。

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY FSM IS
  PORT(
     Clk           : IN  STD_LOGIC;
     nResetLogic   : IN  STD_LOGIC;
     A             : IN  STD_LOGIC;
     B             : IN  STD_LOGIC;
     OUT_A              : OUT STD_LOGIC;
     OUT_B              : OUT STD_LOGIC;
    );
END ENTITY FSM;

ARCHITECTURE RTL OF FSM IS

-- states
TYPE state IS (stateA, stateB, stateC);
signal present_state, next_state : state;

-- Segnals for outputs
signal s_OUT_A              : STD_LOGIC;  
signal s_OUT_B              : STD_LOGIC;  



BEGIN

  -- Sequential section

  PROCESS (nResetLogic, Clk)
  BEGIN

    IF nResetLogic = '0' THEN
      present_state <= stateA;
    ELSIF (RISING_EDGE(Clk)) THEN
      present_state <= next_state;
    END IF;

  END PROCESS;

  -- Comb Section

  PROCESS (A,B,present_state)

  BEGIN
    --defaults
    s_OUT_A <= '0';         
    s_OUT_B <= '0';

    next_state <= present_state;

    CASE present_state IS
        WHEN stateA =>
            -- state definition
            IF (B = '0' AND A = '1') THEN 
                next_state <= stateB;
            ELSIF (B = '1' AND  A = '0') THEN
                next_state <= stateC;
            END IF;

            --output definition
            s_OUT_A <= '0';         
            s_OUT_B <= '1';


        WHEN stateB =>
            -- state definition
            IF (B = '1' AND A = '1') THEN 
                next_state <= stateC;
            ELSIF (B = '1' AND A = '0') THEN 
                next_state <= stateA;

            END IF;

            --output definition
            s_OUT_A <= '1';         
            s_OUT_B <= '1';


        WHEN stateC =>
            -- state definition
            IF (B = '0' AND A = '1') THEN 
                next_state <= statoA;
            ELSIF (B = '1' AND A = '0') THEN
                next_state <= statonB;
            END IF;

            --output definition
            --get defaults        

    END CASE;

  END PROCESS;

  -- Outputs
  OUT_A <= s_OUT_A;         
  OUT_B <= s_OUT_B;  

END ARCHITECTURE RTL;

Answer 3

上面的编码风格有一些很好的评论，但是为了直接回答原始问题，当您布置＆＃39; if＆＃39;时，您的错误非常清楚。很好地陈述：

when S2 =>
    if eq then curr_state := S7;
    else if It then curr_state := S4;
    else if not(eq or It) then curr_state := S3;
    end if;

变为：

when S2 =>
    if eq then
        curr_state := S7;
    else
        if It then
            curr_state := S4;
        else
            if not(eq or It) then
                curr_state := S3;
            end if;

正如你所看到的那样，如果＆＃39;声明。通常，您会发现FPGA工具产生的错误实际上是由前一行中的某些内容引起的。在这种情况下，线条＆＃34;当S3 =＆gt;＆＃34;产生错误，因为你不能有＆＃34;当＆＃34;本身就是一个＆＃34;否则＆＃34;块。

VHDL中的语法错误 - 在case语句中

3 个答案: