我一直在出错。它们被声明为语法错误,但我认为还有其他问题。
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity bottlefill is
port ( clk, reset: IN STD_LOGIC;
b, p: in std_logic;
m, v: out std_logic;
);
end bottlefill;
ARCHITECTURE a of bottlefill is
type state is (stopped, posi, fill);
signal current1, next1: state;
signal c: integer range 0 to 15;
signal full: std_logic;
begin
process(clk, reset)
begin
if reset = '1' then
current1 <= stopped;
elsif clk'event and clk = 1
then current1 <= next1;
end if;
end process;
process(current1, b, p, stop)
begin
next1 <= current1;
case current1 is
when stopped =>
if b = '1' then
next1 <= posi;
end if;
m = '1';
v = '0';
when posi =>
if p = '1' then
next1 <= fill;
end if;
m = '0';
v = '1';
when fill =>
if full = '1' then
next1 <= stopped;
end if;
m = '0';
v = '0';
end case;
end process;
process(clk reset)
begin
if reset = '1'
then c <= 0;
elsif clk'event and clk = '1'
then if current1 = fill
then c <= c + 1;
else
c <= 0;
end if
end process;
full <= '1' when c >= 5
else '0';
信息:命令:quartus_map --read_settings_files = on --write_settings_files = off bottlefill -c bottlefill
中找到0个设计单位,包括0个实体
错误(10500):文本“)”附近的bottlefill.vhd(9)处的VHDL语法错误;需要标识符,“常量”,“文件”,“信号”或“变量”
错误(10500):文本“)”附近的bottlefill.vhd(14)处的VHDL语法错误;期待“:”或“,”
错误(10500):在文本“开始”附近的bottlefill.vhd(19)处发生VHDL语法错误;需要一个标识符(“ begin”是保留关键字),“ constant”,“ file”,“ signal”或“ variable”
错误(10500):文本“)”附近的bottlefill.vhd(29)处的VHDL语法错误;期待“:”或“,”
信息:在源文件bottlefill.vhd
答案 0 :(得分:1)
我已更正了您的代码,使其不再具有语法错误。 您唯一需要检查的就是第68行的代码。我不明白您想要在这里做什么。
我评论了您的语法错误,因此您可以看到导致错误的原因。
希望这对您有所帮助。
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity bottlefill is
port ( clk, reset: IN STD_LOGIC;
b, p: in std_logic;
m, v: out std_logic -- First mistake here
);
end bottlefill;
ARCHITECTURE behavioral of bottlefill is
type state is (stopped, posi, fill);
signal current1, next1: state;
signal c: integer range 0 to 15;
signal full: std_logic;
begin
process(clk, reset)
begin
if reset = '1' then
current1 <= stopped;
elsif clk'event and clk = '1' then -- Mistake with clk = 1 => clk = '1'
current1 <= next1;
end if;
end process;
process(current1, b, p) -- Stop is not declared here
begin
next1 <= current1;
case current1 is
when stopped =>
if b = '1' then
next1 <= posi;
end if;
m <= '1'; -- = is not <= signal assignment !!
v <= '0'; -- = is not <= signal assignment !!
when posi =>
if p = '1' then
next1 <= fill;
end if;
m <= '0'; -- = is not <= signal assignment !!
v <= '1'; -- = is not <= signal assignment !!
when fill =>
if full = '1' then
next1 <= stopped;
end if;
m <= '0'; -- = is not <= signal assignment !!
v <= '0'; -- = is not <= signal assignment !!
end case;
end process;
process(clk, reset) -- komma here
begin
if reset = '1' then
c <= 0;
elsif clk'event and clk = '1' then
if current1 = fill then
c <= c + 1;
else
c <= 0;
end if; -- forgot ;
end if; -- forgot to close the upper is statement
end process;
-- i dont get what u want to do here. Take a look at " Select signal assigment" on google
-- I think you want to do that.
--full <= '1' when c >= 5
--else '0';
end behavioral; -- forgot to end your architecture