环形振荡器

Question

我在实施环形振荡器时遇到了一些麻烦。我不关心它在FPGA上工作。我只想使用Xilinx ISE进行仿真。代码是否可以接受？我还加了测试台。谢谢！

代码

---

library ieee;
use ieee.std_logic_1164.all;

-- 5 Ring Oscillator

entity ring_osc is
    port (ro_en : in std_logic;
            delay : in time;
            ro_out : out std_logic);
end ring_osc;

architecture behavioral of ring_osc is
    signal gate_out : std_logic_vector(5 downto 0) := (others => '0');

begin
    process
    begin
        gate_out(0) <= ro_en and gate_out(5);
        wait for delay;
        gate_out(1) <= not(gate_out(0));
        wait for delay;
        gate_out(2) <= not(gate_out(1));
        wait for delay;
        gate_out(3) <= not(gate_out(2));
        wait for delay;
        gate_out(4) <= not(gate_out(3));
        wait for delay;
        gate_out(5) <= not(gate_out(4));
        wait for delay;
        ro_out <= gate_out(5);
    end process;

end behavioral;

测试台

---

library ieee;
use ieee.std_logic_1164.all;

entity ring_osc_tb is
end ring_osc_tb;

architecture behavior of ring_osc_tb is 

    -- component declaration for the unit under test (uut)

    component ring_osc
        port (ro_en : in  std_logic;
              delay : in time;
              ro_out : out  std_logic);
    end component;


    -- Inputs
    signal ro_en : std_logic := '0';
    signal delay : time := 0.5 ns;

    -- Outputs
    signal ro_out : std_logic;

    signal clk : std_logic := '0';
    constant clk_period : time := 10 ns;

begin

    -- instantiate the unit under test (uut)
    uut: ring_osc port map (
        ro_en => ro_en,
        delay => delay,
        ro_out => ro_out
    );

    -- clock process definitions
    clk_process :process
    begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
    end process;

    -- stimulus process
    stim_proc: process
    begin
        ro_en <= '1';
        delay <= 0.5 ns;
        wait for 10*clk_period;

        delay <= 1 ns;
        wait for 5*clk_period;

        assert false report "End of Simulation" severity failure;
    end process;

end;

Answer 1

顺序wait的流程没有描述Ring oscillator中门的并发性质，因为执行在每个delay暂停wait次，这是不是真正的单词设计的运作方式。

同时评估所有门的描述可以是：

gate_out(0) <= ro_en and gate_out(5) after delay;

inv_g : for i in 1 to gate_out'high generate
  gate_out(i) <= not gate_out(i - 1) after delay;
end generate;

ro_out <= gate_out(5);

由于环形振荡器的固有环路特性，这仅用于仿真，正如问题中所述。

使用测试台，在开始时添加禁用：

-- Disable at start
ro_en <= '0';
delay <= 0.5 ns;
wait for 10 * 0.5 ns;

然后得到的波形为：