Question

我尝试使用yosys（0.7）为ice40 FPGA实现一个简单的环形振荡器，如下所示：

module ringosc(input clkin,
               output out);

   (* keep="true" *)
   wire [100:0]              ring;

   assign ring[100:1] = ~ring[99:0];
   assign ring[0]     = ~ring[100];

   assign out = ring[0];

endmodule

然而，即使我使用keep属性，它似乎也被优化了。我可以在yosys日志输出中看到这个：

7.14.2. Executing OPT_EXPR pass (perform const folding).
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$292' (double_invert) in module `\lfsr' with constant driver `\trng.ring [62] = \trng.ring [60]'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$293' (double_invert) in module `\lfsr' with constant driver `\trng.ring [63] = \trng.ring [59]'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$294' (double_invert) in module `\lfsr' with constant driver `\trng.ring [64] = \trng.ring [58]'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$295' (double_invert) in module `\lfsr' with constant driver `\trng.ring [65] = \trng.ring [57]'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$296' (double_invert) in module `\lfsr' with constant driver `\trng.ring [66] = \trng.ring [56]'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$297' (double_invert) in module `\lfsr' with constant driver `\trng.ring [67] = \trng.ring [55]'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$298' (double_invert) in module `\lfsr' with constant driver `\trng.ring [68] = \trng.ring [54]'.
...

如何阻止yosys这样做？

Answer 1

手动实例化逻辑单元格，就像在此示例项目中完成的那样： http://svn.clifford.at/handicraft/2015/ringosc/

（该项目来自我在2015年制作的视频：
https://www.youtube.com/watch?v=UFqWjZudOho）

Yosys在ice40 FPGA上优化了环形振荡器

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