Question

如何使用读取使能在引脚上正确输出信号？我正在使用ZyBo板并使用FIFO生成器向导。我需要异步，连续写入FIFO并从FIFO读取。这就是我需要write_enable信号和read_enable信号的原因。但是，我无法从FIFO读取。我检查以确保FIFO不是空的并且read_enable被断言。我通过将32位字序列化到数据引脚上来读取FIFO。（它从串行化到引脚I和引脚Q交替）。如何确保从FIFO中读取并将串行数据输出到引脚上？以下是我的代码：

// Wires and registers related to data capturing 
wire        capture_clk;
reg [31:0]  capture_data;
wire        capture_en;
reg [4:0]   slowdown;
wire        capture_full;

reg            capture_open;
reg            capture_open_cross;
reg            capture_has_been_full;
reg            capture_has_been_nonfull;
reg            has_been_full_cross;
reg            has_been_full;

// Data capture section
// ====================

always @(posedge capture_clk)
  begin
if (capture_en)
  capture_data <= user_w_write_32_data; // Data source being read from a file

// The slowdown register limits the data pace to 1/32 the bus_clk
// when capture_clk = bus_clk. This is necessary, because the
// core in the evaluation kit is configured for simplicity, and
// not for performance. Sustained data rates of 200 MB/sec are
// easily reached with performance-oriented setting.
// The slowdown register has no function in a real-life application.
slowdown <= slowdown + 1;

// capture_has_been_full remembers that the FIFO has been full
// until the file is closed. capture_has_been_nonfull prevents
// capture_has_been_full to respond to the initial full condition
// every FIFO displays on reset.

if (!capture_full)
  capture_has_been_nonfull <= 1;
else if (!capture_open)
  capture_has_been_nonfull <= 0;

if (capture_full && capture_has_been_nonfull)
  capture_has_been_full <= 1;
else if (!capture_open)
  capture_has_been_full <= 0;

  end

// The dependency on slowdown is only for bogus data
assign capture_en = capture_open && !capture_full && 
             !capture_has_been_full &&
             (slowdown == 0);

// Clock crossing logic: bus_clk -> capture_clk
always @(posedge capture_clk)
  begin
capture_open_cross <= user_r_read_32_open;
capture_open <= capture_open_cross;
  end

// Clock crossing logic: capture_clk -> bus_clk
always @(posedge bus_clk)
  begin
has_been_full_cross <= capture_has_been_full;
has_been_full <= has_been_full_cross;
  end

// The user_r_read_32_eof signal is required to go from '0' to '1' only on
// a clock cycle following an asserted read enable, according to Xillybus'
// core API. This is assured, since it's a logical AND between
// user_r_read_32_empty and has_been_full. has_been_full goes high when the
// FIFO is full, so it's guaranteed that user_r_read_32_empty is low when
// that happens. On the other hand, user_r_read_32_empty is a FIFO's empty
// signal, which naturally meets the requirement.

assign user_r_read_32_eof = user_r_read_32_empty && has_been_full;
assign user_w_write_32_full = 0;

// The data capture clock here is bus_clk for simplicity, but clock domain
// crossing is done properly, so capture_clk can be an independent clock
// without any other changes.

assign capture_clk = bus_clk;

async_fifo_32x512 fifo_32 //FIFO created using Xilinx FIFO Generator Wizard
  (
    .rst(!user_r_read_32_open),
    .wr_clk(capture_clk),
    .rd_clk(bus_clk),
    .din(capture_data),
    .wr_en(capture_en),
    .rd_en(user_r_read_32_rden),
    .dout(user_r_read_32_data),
    .full(capture_full),
    .empty(user_r_read_32_empty)
    );

    reg Q_en = 1'b0; //starting value is 0 because first 32bit is I
    reg [31:0] data_outI = 32'd0;
    reg [31:0] data_outQ = 32'd0;
    reg I = 1'b0;
    reg Q = 1'b0;
    reg counter_32_shift = 6'b000000;
    reg temp = 1'b0;

    always @(posedge bus_clk) begin
        if(user_r_read_32_empty == 1'b0 && user_r_read_32_rden == 1'b1)begin //if something in FIFO
            if(Q_en == 1'b0) begin //output onto pin I
                if(counter_32_shift == 6'b000000) begin
                    data_outI <= user_r_read_32_data;
                end else if(counter_32_shift != 5'd32) begin
                    I <= data_outI[0];
                    data_outI <= (data_outI >> 1);
                    Q <= data_outQ[0];
                    data_outQ <= (data_outQ >> 1);
                    counter_32_shift <= counter_32_shift + 1'b1;
                end else begin //counter_32_shift == 32
                    I <= data_outI[0];
                    data_outI <= (data_outI >> 1);
                    Q <= data_outQ[0];
                    data_outQ <= (data_outQ >> 1);
                    counter_32_shift <= 6'd0;
                    Q_en <= ~Q_en;
                end
            end else if(Q_en == 1'b1) begin //Output onto pin Q
                if(counter_32_shift == 6'd0) begin
                    data_outQ <= user_r_read_32_data;
                end else if(counter_32_shift != 6'd32) begin
                    I <= data_outI[0];
                    data_outI <= (data_outI >> 1);
                    Q <= data_outQ[0];
                    data_outQ <= (data_outQ >> 1);
                    counter_32_shift <= counter_32_shift + 1'b1;
                end else begin //counter_32_shift == 32
                    I = data_outI[0];
                    data_outI <= (data_outI >> 1);
                    Q = data_outQ[0];
                    data_outQ <= (data_outQ >> 1);
                    counter_32_shift <= 6'd0;
                    Q_en <= ~Q_en;
                end
            end// end Q_en compare
        end //end check if FIFO empty
    end //end always

提前致谢所有帮助

Answer 1

您需要更好地设计编写时钟逻辑的方式。

例如，在您的代码中，如果fifo不为空，则只写入I和Q，这是不正确的。

您需要一个以下模块：

从fifo获取32位值，存储它，然后将其串行化为一个超过32个周期的引脚。
一旦从fifo中读入了一个值，无论fifo是否为空，它都需要保持序列化（当你在新的32-中时，你只关心fifo的状态 - 位值）。
仅在当前未进行序列化时接受新值。

自上一个问题以来，设计看起来一直在取得进展，但你还没有得到正确的逻辑。尝试使用波形调试器来更好地理解为什么它没有按照您期望的方式工作。

verilog异步FIFO向导

1 个答案: