Question

我有以下代码，我尝试在verilog中实现低延迟的第一个单词fall-through fifo。

   reg [width-1:0]       mem [depth-1:0];

   always @ (posedge clk) begin
      if (wr_en) begin
         mem[wr_pointer[address_width-1:0]] <= #1 din;
      end
   end

   assign #1 dout = mem[rd_pointer[address_width-1:0]];

   always @ (posedge clk) begin
      if (reset) begin
         wr_pointer <= #1 0;
      end else if (wr_en) begin
         wr_pointer <= #1 wr_pointer + 1'b1;
      end
   end

   always @ (posedge clk) begin
      if (reset) begin
         rd_pointer <= #1 0;
      end else if (rd_en) begin
         rd_pointer <= #1 rd_pointer + 1'b1;
      end
   end

我合成它并收到以下消息：

INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_mem> will be implemented on LUTs 
either because you have described an asynchronous read or because of currently
unsupported block RAM features. If you have described an asynchronous read, 
making it synchronous would allow you to take advantage of available block RAM
resources, for optimized device usage and improved timings. Please refer to 
your documentation for coding guidelines.

有人可以向我解释这条消息吗？我不相信这需要异步读取。我只修改时钟边沿的读指针。还有其他事情发生在我身上吗？

Answer 1

以下行是您的异步读取：

assign #1 dout = mem[rd_pointer[address_width-1:0]];

将其更改为类似下面的代码，以使其同步。

reg [width-1:0] dout;
always @ (posedge clk) begin
   if (reset) begin
      dout <= #1 0;
   end else if (rd_en) begin
      dout <= #1 mem[rd_pointer[address_width-1:0]]
   end
end

您所拥有的异步读取意味着内存中的所有字必须随时可用，因为内存地址可能随时发生变化（而不仅仅是在时钟边缘）。

由于异步读取需要访问所有存储器字，因此FPGA无法使用片上RAM。片上RAM具有读总线，该总线只能访问存储器中的一个字，并且在时钟边沿上发生变化。因此，建立内存而不是一堆LUT。在这种情况下，您可以将内存视为来自2D触发器阵列的构建，现在它可以连接到所有单词。

Verilog中的低延迟FWFT Fifo

1 个答案: