Question

module ram_1_verilog(input EnA,input EnB,
  input WeA, input WeB,
  input Oe,
  input clk);

LINE :25   input [7:0] Addr_a;      //Error
LINE :26   input [7:0]Addr_b;       //Error
LINE :27   input reg [7:0] dout1;   //Error
LINE :28   output reg [7:0] dout_2; //Error

reg [7:0] ram [255:0];

always @(posedge clk)
begin
  if(EnA == 1 && WeA == 1) begin 
LINE 35  ram(Addr_a) <= dout1;      //Error 
  end
end

always @(posedge clk)
begin
  if(EnB == 1 && WeB == 0) begin
  LINE : 44 dout_2 <= ram(Addr_b);  //Error
  end
end
endmodule

错误：

Syntax error near "<=". line 35
Line 25: Port Addr_a is not defined Verilog file C:/Documents and Settings/verilog_examples/ram_1_verilog.v ignored due to errors
Line 25: Port declaration not allowed in ram_1_verilog with formal port declaration list
Line 26: Port Addr_b is not defined
Line 26: Port Addr_b is not defined
Line 26: Port declaration not allowed in ram_1_verilog with formal port declaration list
Line 27: Port dout1 is not defined

Line 27: Non-net port dout1 cannot be of mode input
Line 27: Port declaration not allowed in ram_1_verilog with formal port declaration list
Line 28: Port dout_2 is not defined
Line 28: Port declaration not allowed in ram_1_verilog with formal port declaration list
Line 35: dout1 is not a task

Line 44: ram is not a function.
Line 44: ram expects 0 arguments.
Line 44: Cannot assign an unpacked type to a packed type.

我正在研究一个dpram，它在vhdl中使用相同的逻辑工作正常，但在verilog中出错，请帮我弄清楚错误是什么。

Answer 1

我看到的一个问题是你在尝试使用括号进行数组选择时应该使用方括号：

更改自：

LINE 35         ram(Addr_a) <= dout1;       // error

为：

LINE 35         ram[Addr_a] <= dout1;

我没有在第25-28行看到任何错误，也不确定为何会被标记。

Answer 2

第35和44行 - 你犯了两次同样的错误，Tim给你解释。
第25-28行被标记，因为Addr_a，Addr_b，dout1和dout_2未在端口声明列表中声明，然后被定义为{{1} } / input。

我是verilog的新手，请帮我弄清楚可能是什么错误

2 个答案: