为什么clk_divider不工作？

Question

代码是：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity clk_div is
Port (
         clk_in                      : in  STD_LOGIC;
         clk_out_rx              : out std_logic;
         out_bit_parity          : out std_logic
     ); 
end clk_div;
architecture Behavioral of clk_div is
signal clk_slow_tx : std_logic := '0';
signal q : unsigned(9 downto 0) := (others => '0');
begin

process ( clk_in ) is 
begin 
if rising_edge(clk_in) then
q <= q + 1;
clk_slow_tx <= q(8);   --- 58.gdfg/2^8 =~ 230Khz baud rate = 115200 
clk_out_rx <= clk_slow_tx;
end if;
end process;
end Behavioral;

我正在添加上述代码的测试平台波形： 如果你需要测试平台代码我也可以写。

Answer 1

模块中未分配输出out_bit_parity，但其他输出clk_out_rx切换正常：

根据要求在下面添加测试台：

library ieee;
use ieee.std_logic_1164.all;

entity mdl_tb is
end entity;


library ieee;
use ieee.numeric_std.all;

architecture sim of mdl_tb is

  constant CLK_FREQ : real := 100.0E6;  -- Clock frequency in Hz
  signal clk        : std_logic;

  signal dut_clk_out_rx     : std_logic;
  signal dut_out_bit_parity : std_logic;

begin

  process is
  begin
    while TRUE loop
      clk <= '1';
      wait for 0.5 sec / CLK_FREQ;
      clk <= '0';
      wait for (1.0 sec / CLK_FREQ) - (0.5 sec / CLK_FREQ);
    end loop;
  end process;

  mdl_e : entity work.clk_div
    port map(
      clk_in => clk,
      clk_out_rx => dut_clk_out_rx,
      out_bit_parity => dut_out_bit_parity);

end architecture;