Question

我在第90行有一个错误

90     std_logic_vector( unsigned(a)+ unsigned(b) ) when (arth_sel)="0000" else

我的代码是：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Arth is
    Port (signal arth_sel : in  STD_LOGIC_VECTOR (3 downto 0);
           a : in  STD_LOGIC_VECTOR (15 downto 0);
           b : in  STD_LOGIC_VECTOR (15 downto 0);
           c : in  STD_LOGIC_VECTOR(0 downto 0);
           result : out  STD_LOGIC_VECTOR (16 downto 0));
end Arth;
architecture Behavioral of Arth is
--das_result : std_logic_vector(15 downto 0);
signal a_lower :std_logic_vector(7 downto 0) := a(7 downto 0);
signal b_lower :std_logic_vector(7 downto 0) := b(7 downto 0);
signal sum_temp1_lower : std_logic_vector(7 downto 0);
signal sum_temp1_upper : std_logic_vector(7 downto 0);
signal sum_temp1 : std_logic_vector(15 downto 0);
signal sum_temp2: std_logic_vector(7 downto 0);

signal daa_result: std_logic_vector(15 downto 0); 

begin
sum_temp1 <= std_logic_vector(unsigned(a) + unsigned(b));
sum_temp2 <= std_logic_vector(unsigned(a_lower)+unsigned(b_lower));
sum_temp1_lower <= sum_temp1(7 downto 0);
sum_temp1_upper <= sum_temp1(15 downto 8);
process(a,b) 
begin
if ( unsigned(sum_temp1_upper) >9 and unsigned(sum_temp1_lower) >9) then
sum_temp1<= std_logic_vector(unsigned(sum_temp1)+66);
elsif( unsigned(sum_temp1_lower) > 9 or sum_temp2(7)='1') then
sum_temp1 <= std_logic_vector(unsigned(sum_temp1)+6) ;
elsif (unsigned(sum_temp1_upper) > 9) then
sum_temp1<= std_logic_vector(unsigned(sum_temp1)+60);
end if;
daa_result<= sum_temp1;
end process;   
result <=    
    std_logic_vector( unsigned(a)+ unsigned(b) ) when (arth_sel)="0000" else
    std_logic_vector( unsigned(a)+ unsigned(b)) when (arth_sel)="0001" else
    std_logic_vector( unsigned(a)+ unsigned(b) + unsigned(c)) when (arth_sel)="0010" else
    std_logic_vector( unsigned(a)+1)when (arth_sel)="0011" else
    std_logic_vector( unsigned(a)- unsigned(b))when (arth_sel)="0100" else
    std_logic_vector( unsigned(a)- unsigned(b))when (arth_sel)="0101" else
    std_logic_vector( unsigned(a)- unsigned(b) - unsigned(c))when (arth_sel)="0110" else
    std_logic_vector( unsigned(a)- 1)when (arth_sel)="0111" else
    std_logic_vector( unsigned(a)* unsigned(b))when (arth_sel)="1000" else
    std_logic_vector( signed(a)* signed(b))when (arth_sel)="1001" else
    std_logic_vector( unsigned(a)- unsigned(b))when (arth_sel)="1010" else 

    std_logic_vector( unsigned(a)- unsigned(b))when (arth_sel)="1011" else  std_logic_vector( unsigned(not(a))+1)when (arth_sel)="1100" else
    daa_result when(arth_sel)="1101"  else 

  (others => 'X'); 

end Behavioral;

我真的不知道出了什么问题:(我提到了这个话题vhdl: Xilinx code error，但它并没有解决我的问题。提前谢谢。

Answer 1

问题在于选择：

result <=   ...
            daa_result when(arth_sel)="1101"  else

其中一件事情与另一件事情不同：

          result : out  STD_LOGIC_VECTOR (16 downto 0));

signal daa_result: std_logic_vector(15 downto 0);

具体而言，是范围所暗示的长度。

目前还不清楚daa意味着什么，你可以：

            '0'& daa_result when(arth_sel)="1101"  else

将长度增加到17，匹配结果。

顺便说一句：

signal a_lower :std_logic_vector(7 downto 0) := a(7 downto 0);
signal b_lower :std_logic_vector(7 downto 0) := b(7 downto 0);

不是分别将a和b的低8位分配给a_lower和b_lower的方法。此默认值分配仅在发出这两个信号的声明时生效，并且将全部为“

”。

您可以添加并发信号分配语句：

begin

    a_lower <= a(7 downto 0);
    b_lower <= b(7 downto 0);

（在架构开始之后）。

c可以声明为非数组类型：

    c:          in  std_logic; -- _vector (0 downto 0);

需要一些VHDL legerdemain：

result <=    
    std_logic_vector(unsigned(a) + unsigned(b)) when arth_sel = "0000" else
    std_logic_vector(unsigned(a) + unsigned(b)) when arth_sel = "0001" else
    std_logic_vector(unsigned(a) + unsigned(b) 
                           + unsigned'(c & "")) when arth_sel = "0010" else
    std_logic_vector(unsigned(a) + 1)           when arth_sel = "0011" else
    std_logic_vector(unsigned(a) - unsigned(b)) when arth_sel = "0100" else
    std_logic_vector(unsigned(a) - unsigned(b)) when arth_sel = "0101" else
    std_logic_vector(unsigned(a) - unsigned(b) 
                           - unsigned'(c & "")) when arth_sel = "0110" else
    std_logic_vector(unsigned(a) - 1)           when arth_sel = "0111" else
    std_logic_vector(unsigned(a) * unsigned(b)) when arth_sel = "1000" else
    std_logic_vector(signed(a)   * signed(b))   when arth_sel = "1001" else
    std_logic_vector(unsigned(a) - unsigned(b)) when arth_sel = "1010" else 

    std_logic_vector(unsigned(a) - unsigned(b)) when arth_sel = "1011" else
    std_logic_vector(unsigned(not(a))+1)        when arth_sel = "1100" else
    '0' & daa_result                            when arth_sel = "1101" else
    (others => 'X');

unsigned'(c & "")将c与零长度字符串连接起来，并将得到的数组类型限定为无符号。

xilinx中条件信号分配中分配的元素数量不匹配

1 个答案: