Question

我为我的16位MIPS架构写了一个寄存器文件，在这里我确保我的register0包含全零，没有语法错误，但我有一些问题

我是否完成了类型转换？因为我得到一些关于生成锁存器的警告。我在这做错了什么？

另外conv_integer和to_integer（unsigned（（w_addr））有什么区别？因为当我使用to_integer（unsigned（r_addr1）= 0）时，我遇到了错误。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;


entity regfile is
generic(
N: integer:=4; --number of bits for address
W: integer:=16 --number of bits
);
 Port ( clk : in  STD_LOGIC;
   w_en : in  STD_LOGIC;
   r_addr1,r_addr2,w_addr : in  STD_LOGIC_VECTOR (N-1 downto 0);
   w_data: in STD_LOGIC_VECTOR (W-1 downto 0);
      r_data1, r_data2  : out  STD_LOGIC_VECTOR (W-1 downto 0));
end regfile;

   architecture Behavioral of regfile is
   type regfile_type is array (W-1 downto 0) of STD_LOGIC_VECTOR (W-1 downto 0);
   signal RegisterFile: regfile_type;
   begin
   process(clk)
   begin
if (clk = '1') then
    if (w_en = '1') then
        RegisterFile(to_integer(unsigned(w_addr))) <= w_data;
    end if;
end if;
  end process;
     process (r_addr1, r_addr2)     
begin
    if (conv_integer(r_addr1)=0) then
        r_data1 <= X"0000";
            else r_data1<=RegisterFile(to_integer(unsigned(r_addr1)));
    end if;
    if (conv_integer(r_addr2)=0) then 
        r_data2 <= X"0000";
            else r_data2 <= RegisterFile(to_integer(unsigned(r_addr2)));
    end if;
   end process;
    end Behavioral;

这些是我得到的警告

WARNING:Xst:819 - "E:/Xilinx Projects/regfile/regfile.vhd" line 49: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:<w_en>, <w_data>
WARNING:Xst:819 - "E:/Xilinx Projects/regfile/regfile.vhd" line 58: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <RegisterFile>
WARNING:Xst:737 - Found 16-bit latch for signal <RegisterFile_15>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <RegisterFile_14>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <RegisterFile_13>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <RegisterFile_12>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <RegisterFile_11>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

Answer 1

1。该行：

if (clk = '1') then

应该是：

if (clk'event and clk = '1') then

或：

if rising_edge(clk) then

这是您的锁存器的创建位置。虽然灵敏度列表似乎可以隐含该事件，但需要明确合成工具正确推断触发器。

2。 to_integer(unsigned(r_addr1)=0) - 您的意思是to_integer(unsigned(r_addr1))=0（应该可以正常工作）？小心匹配括号。顺便说一句，unsigned只比较整数文字，所以你不需要to_integer。只需unsigned(r_addr1)=0即可。

Answer 2

您的计时过程未正确写入。工具没有意识到clk实际上是一个时钟。您需要使用clk＆＃39;事件或更好地使用rising_edge（）。这些工具正在创建一个组合过程，而不是顺序过程。由于if语句中没有其他条件，因此它使RegisterFile成为一个锁存器。以下是what is a latch and how to avoid latches in your FPGA

的更多信息

process(clk)
begin
  if rising_edge(clk) then
    if w_en = '1' then
      RegisterFile(to_integer(unsigned(w_addr))) <= w_data;
    end if;
  end if;
end process;

生成VHDL双端口RAM意外锁存器

2 个答案: