我无法在裸机项目内的德州仪器（TI）的ICE评估板上为DDR2内存初始化EMIF和DDR_PHY。 我根据StarterWare bootloader示例中的序列编写了一个init序列。但是我不能让DDR工作。
控制器贯穿整个过程，但DDR在调试器中的每一步都看起来都是随机的。我正在监控0x80000000。使用调试器写入此区域也不起作用。状态寄存器显示PHY未就绪。
我错过了什么吗？我是否有一个或另一个命令的错误序列？ 有人可以提供建议吗？
这是我的代码：
{
//! Switch to System Mode
asm(" swi #1;");
//! Enable EMIF
CM_PER->EMIF_FW_CLKCTRL |= 2;
CM_PER->EMIF_CLKCTRL |= 2;
while (!(CM_PER->L3_CLKSTCTRL & ((1 << 4) | (1 << 2))));
//! Phy init
CONTROL_MODULE->VTP_CTRL |= (1 << 6);
CONTROL_MODULE->VTP_CTRL &= ~(1 << 0);
CONTROL_MODULE->VTP_CTRL |= (1 << 0);;
while (!(CONTROL_MODULE->VTP_CTRL & (1 << 5)));
DDR_PHY->CMD[0].SLAVE_RATIO = DDR_CONFIG_PHY_CMD0_SLAVE_RATIO;
DDR_PHY->CMD[0].SLAVE_FORCE = DDR_CONFIG_PHY_CMD0_SLAVE_FORCE;
DDR_PHY->CMD[0].SLAVE_DELAY = DDR_CONFIG_PHY_CMD0_SLAVE_DELAY;
DDR_PHY->CMD[0].DLL_LOCK_DIFF = DDR_CONFIG_PHY_CMD0_LOCK_DIFF;
DDR_PHY->CMD[0].INVERT_CLKOUT = DDR_CONFIG_PHY_CMD0_INVERT_CLKOUT;
DDR_PHY->CMD[1].SLAVE_RATIO = DDR_CONFIG_PHY_CMD1_SLAVE_RATIO;
DDR_PHY->CMD[1].SLAVE_FORCE = DDR_CONFIG_PHY_CMD1_SLAVE_FORCE;
DDR_PHY->CMD[1].SLAVE_DELAY = DDR_CONFIG_PHY_CMD1_SLAVE_DELAY;
DDR_PHY->CMD[1].DLL_LOCK_DIFF = DDR_CONFIG_PHY_CMD1_LOCK_DIFF;
DDR_PHY->CMD[1].INVERT_CLKOUT = DDR_CONFIG_PHY_CMD1_INVERT_CLKOUT;
DDR_PHY->CMD[2].SLAVE_RATIO = DDR_CONFIG_PHY_CMD2_SLAVE_RATIO;
DDR_PHY->CMD[2].SLAVE_FORCE = DDR_CONFIG_PHY_CMD2_SLAVE_FORCE;
DDR_PHY->CMD[2].SLAVE_DELAY = DDR_CONFIG_PHY_CMD2_SLAVE_DELAY;
DDR_PHY->CMD[2].DLL_LOCK_DIFF = DDR_CONFIG_PHY_CMD2_LOCK_DIFF;
DDR_PHY->CMD[2].INVERT_CLKOUT = DDR_CONFIG_PHY_CMD2_INVERT_CLKOUT;
DDR_PHY->DATA[0].RD_DQS_SLAVE_RATIO = DDR_CONFIG_PHY_DATA0_RD_DQS_SLAVE_RATIO;
DDR_PHY->DATA[0].WR_DQS_SLAVE_RATIO = DDR_CONFIG_PHY_DATA0_WR_DQS_SLAVE_RATIO;
DDR_PHY->DATA[0].FIFO_WE_SLAVE_RATIO = DDR_CONFIG_PHY_DATA0_FIFO_WE_SLAVE_RATIO;
DDR_PHY->DATA[0].WR_DATA_SLAVE_RATIO = DDR_CONFIG_PHY_DATA0_WR_DATA_SLAVE_RATIO;
DDR_PHY->DATA[1].RD_DQS_SLAVE_RATIO = DDR_CONFIG_PHY_DATA1_RD_DQS_SLAVE_RATIO;
DDR_PHY->DATA[1].WR_DQS_SLAVE_RATIO = DDR_CONFIG_PHY_DATA1_WR_DQS_SLAVE_RATIO;
DDR_PHY->DATA[1].FIFO_WE_SLAVE_RATIO = DDR_CONFIG_PHY_DATA1_FIFO_WE_SLAVE_RATIO;
DDR_PHY->DATA[1].WR_DATA_SLAVE_RATIO = DDR_CONFIG_PHY_DATA1_WR_DATA_SLAVE_RATIO;
//! Set control registers
CONTROL_MODULE->DDR_CMD0_IOCTRL = DDR_CONFIG_CMD0_IOCTRL;
CONTROL_MODULE->DDR_CMD1_IOCTRL = DDR_CONFIG_CMD1_IOCTRL;
CONTROL_MODULE->DDR_CMD2_IOCTRL = DDR_CONFIG_CMD2_IOCTRL;
CONTROL_MODULE->DDR_DATA0_IOCTRL = DDR_CONFIG_DATA0_IOCTRL;
CONTROL_MODULE->DDR_DATA1_IOCTRL = DDR_CONFIG_DATA1_IOCTRL;
CONTROL_MODULE->DDR_IO_CTRL &= DDR_CONFIG_IOCTRL;
CONTROL_MODULE->DDR_CKE_CTRL |= DDR_CONFIG_CKE_CTRL;
//! Set memory interface control registers
EMIF0->DDR_PHY_CTRL_1 = DDR_CONFIG_PHY_CTRL_1;
EMIF0->DDR_PHY_CTRL_1 |= DDR_CONFIG_DYN_PWRDN;
EMIF0->DDR_PHY_CTRL_1_SHDW = DDR_CONFIG_PHY_CTRL_1_SHDW;
EMIF0->DDR_PHY_CTRL_1_SHDW |= DDR_CONFIG_DYN_PWRDN_SHDW;
EMIF0->DDR_PHY_CTRL_2 = DDR_CONFIG_PHY_CTRL_2;
//! Set memory interface timing registers
EMIF0->SDRAM_TIM_1 = DDR_CONFIG_SD_TIM_1;
EMIF0->SDRAM_TIM_1_SHDW = DDR_CONFIG_SD_TIM_1_SHDW;
EMIF0->SDRAM_TIM_2 = DDR_CONFIG_SD_TIM_2;
EMIF0->SDRAM_TIM_2_SHDW = DDR_CONFIG_SD_TIM_2_SHDW;
EMIF0->SDRAM_TIM_3 = DDR_CONFIG_SD_TIM_3;
EMIF0->SDRAM_TIM_3_SHDW = DDR_CONFIG_SD_TIM_3_SHDW;
EMIF0->SDRAM_CONFIG = DDR_CONFIG_SD_CONFIG_BEFORE;
EMIF0->SDRAM_REF_CTRL = DDR_CONFIG_SD_REF_CTRL_BEFORE;
EMIF0->SDRAM_REF_CTRL_SHDW = DDR_CONFIG_SD_REF_CTRL_SHDW_BEFORE;
//! Wait for changes to take effect
uint32_t ulDelay = DDR_CONFIG_DELAY_INTERVAL;
while(ulDelay--);
EMIF0->SDRAM_REF_CTRL = DDR_CONFIG_SD_REF_CTRL_AFTER;
EMIF0->SDRAM_REF_CTRL_SHDW = DDR_CONFIG_SD_REF_CTRL_SHDW_AFTER;
EMIF0->ZQ_CONFIG = DDR_CONFIG_ZQ;
EMIF0->SDRAM_CONFIG = DDR_CONFIG_SD_CONFIG_AFTER;
CONTROL_MODULE->CONTROL_EMIF_SDRAM_CONFIG = DDR_CONFIG_SD_CONFIG_AFTER;
//! Switch to User Mode
asm(" swi #0;");
}
设置了以下#defines：
#define DDR_CONFIG_PHY_CMD0_SLAVE_RATIO (0x00000080UL)
#define DDR_CONFIG_PHY_CMD0_SLAVE_FORCE (0x00000000UL)
#define DDR_CONFIG_PHY_CMD0_SLAVE_DELAY (0x00000000UL)
#define DDR_CONFIG_PHY_CMD0_LOCK_DIFF (0x00000000UL)
#define DDR_CONFIG_PHY_CMD0_INVERT_CLKOUT (0x00000000UL)
#define DDR_CONFIG_PHY_CMD1_SLAVE_RATIO (0x00000080UL)
#define DDR_CONFIG_PHY_CMD1_SLAVE_FORCE (0x00000000UL)
#define DDR_CONFIG_PHY_CMD1_SLAVE_DELAY (0x00000000UL)
#define DDR_CONFIG_PHY_CMD1_LOCK_DIFF (0x00000000UL)
#define DDR_CONFIG_PHY_CMD1_INVERT_CLKOUT (0x00000000UL)
#define DDR_CONFIG_PHY_CMD2_SLAVE_RATIO (0x00000080UL)
#define DDR_CONFIG_PHY_CMD2_SLAVE_FORCE (0x00000000UL)
#define DDR_CONFIG_PHY_CMD2_SLAVE_DELAY (0x00000000UL)
#define DDR_CONFIG_PHY_CMD2_LOCK_DIFF (0x00000000UL)
#define DDR_CONFIG_PHY_CMD2_INVERT_CLKOUT (0x00000000UL)
#define DDR_CONFIG_PHY_DATA0_RD_DQS_SLAVE_RATIO (0x00000012UL)
#define DDR_CONFIG_PHY_DATA0_WR_DQS_SLAVE_RATIO (0x00000000UL)
#define DDR_CONFIG_PHY_DATA0_FIFO_WE_SLAVE_RATIO (0x00000080UL)
#define DDR_CONFIG_PHY_DATA0_WR_DATA_SLAVE_RATIO (0x00000040UL)
#define DDR_CONFIG_PHY_DATA1_RD_DQS_SLAVE_RATIO (0x00000012UL)
#define DDR_CONFIG_PHY_DATA1_WR_DQS_SLAVE_RATIO (0x00000000UL)
#define DDR_CONFIG_PHY_DATA1_FIFO_WE_SLAVE_RATIO (0x00000080UL)
#define DDR_CONFIG_PHY_DATA1_WR_DATA_SLAVE_RATIO (0x00000040UL)
#define DDR_CONFIG_CMD0_IOCTRL (0x0000018BUL)
#define DDR_CONFIG_CMD1_IOCTRL (0x0000018BUL)
#define DDR_CONFIG_CMD2_IOCTRL (0x0000018BUL)
#define DDR_CONFIG_DATA0_IOCTRL (0x0000018BUL)
#define DDR_CONFIG_DATA1_IOCTRL (0x0000018BUL)
#define DDR_CONFIG_IOCTRL (0x0FFFFFFFUL)
#define DDR_CONFIG_CKE_CTRL (0x00000001UL)
#define DDR_CONFIG_PHY_CTRL_1 (0x00000005UL)
#define DDR_CONFIG_DYN_PWRDN (0x00000000UL)
#define DDR_CONFIG_PHY_CTRL_1_SHDW (0x00000005UL)
#define DDR_CONFIG_DYN_PWRDN_SHDW (0x00000000UL)
#define DDR_CONFIG_PHY_CTRL_2 (0x00000005UL)
#define DDR_CONFIG_SD_TIM_1 (0x0666B3C9UL)
#define DDR_CONFIG_SD_TIM_1_SHDW (0x0666B3C9UL)
#define DDR_CONFIG_SD_TIM_2 (0x243631CAUL)
#define DDR_CONFIG_SD_TIM_2_SHDW (0x243631CAUL)
#define DDR_CONFIG_SD_TIM_3 (0x0000033FUL)
#define DDR_CONFIG_SD_TIM_3_SHDW (0x0000033FUL)
#define DDR_CONFIG_SD_CONFIG_BEFORE (0x41805332UL)
#define DDR_CONFIG_SD_REF_CTRL_BEFORE (0x00004650UL)
#define DDR_CONFIG_SD_REF_CTRL_SHDW_BEFORE (0x00004650UL)
#define DDR_CONFIG_DELAY_INTERVAL (5000UL)
#define DDR_CONFIG_SD_CONFIG_AFTER (0x41805332UL)
#define DDR_CONFIG_SD_REF_CTRL_AFTER (0x0000081AUL)
#define DDR_CONFIG_SD_REF_CTRL_SHDW_AFTER (0x0000081AUL)
#define DDR_CONFIG_ZQ (0x00000000UL)
答案 0 :(得分：1)
问题解决了......
我经历了现有的初始化并遇到了这样的事实，显然有些寄存器不需要设置。在我的代码中，我仍然使用默认值为完整性设置它们。一般来说，如果我需要在某种后期项目中配置它们，并且可能附加了不同的RAM，请将它们放在一边。我永远不会想到这样做会破坏一些东西。但显然这样做了。我从设置中取出了所有不需要的寄存器，并编写了必要的寄存器，并且工作正常！此外，我放弃了两阶段SDRAM_CONTROL和SDRAM_REF_CTRL设置，在延迟后将设置更改为最终值。我直接拿了最终值。
此代码有效：
//! Switch to System Mode
asm(" swi #1;");
//! Enable EMIF
CM_PER->EMIF_CLKCTRL = 2;
//! Poll for functional peripheral
while (CM_PER->EMIF_CLKCTRL != 2);
//! Enable VTP
CONTROL_MODULE->VTP_CTRL = 0;
CONTROL_MODULE->VTP_CTRL = 6;
CONTROL_MODULE->VTP_CTRL |= (1 << 6);
CONTROL_MODULE->VTP_CTRL &= ~(1 << 0);
CONTROL_MODULE->VTP_CTRL |= (1 << 0);
//! Poll for VTP ready
while (!(CONTROL_MODULE->VTP_CTRL & (1 << 5)));
//! Configure DDR Phy command macros
DDR_PHY->CMD[0].SLAVE_RATIO = DDR_CONFIG_PHY_CMD0_SLAVE_RATIO;
DDR_PHY->CMD[0].INVERT_CLKOUT = DDR_CONFIG_PHY_CMD0_INVERT_CLKOUT;
DDR_PHY->CMD[1].SLAVE_RATIO = DDR_CONFIG_PHY_CMD1_SLAVE_RATIO;
DDR_PHY->CMD[1].INVERT_CLKOUT = DDR_CONFIG_PHY_CMD1_INVERT_CLKOUT;
DDR_PHY->CMD[2].SLAVE_RATIO = DDR_CONFIG_PHY_CMD2_SLAVE_RATIO;
DDR_PHY->CMD[2].INVERT_CLKOUT = DDR_CONFIG_PHY_CMD2_INVERT_CLKOUT;
//! Configure DDR Phy data macros
DDR_PHY->DATA[0].RD_DQS_SLAVE_RATIO[0] = DDR_CONFIG_PHY_DATA0_RD_DQS_SLAVE_RATIO;
DDR_PHY->DATA[0].WR_DQS_SLAVE_RATIO[0] = DDR_CONFIG_PHY_DATA0_WR_DQS_SLAVE_RATIO;
DDR_PHY->DATA[0].WRLVL_INIT_RATIO[0] = DDR_CONFIG_PHY_DATA0_WRLVL_INIT_RATIO;
DDR_PHY->DATA[0].GATELVL_INIT_RATIO[0] = DDR_CONFIG_PHY_DATA0_GATELVL_INIT_RATIO;
DDR_PHY->DATA[0].FIFO_WE_SLAVE_RATIO[0] = DDR_CONFIG_PHY_DATA0_FIFO_WE_SLAVE_RATIO;
DDR_PHY->DATA[0].WR_DATA_SLAVE_RATIO[0] = DDR_CONFIG_PHY_DATA0_WR_DATA_SLAVE_RATIO;
DDR_PHY->DATA[0].DLL_LOCK_DIFF = DDR_CONFIG_PHY_DATA0_DLL_LOCK_DIFF;
DDR_PHY->DATA[1].RD_DQS_SLAVE_RATIO[0] = DDR_CONFIG_PHY_DATA1_RD_DQS_SLAVE_RATIO;
DDR_PHY->DATA[1].WR_DQS_SLAVE_RATIO[0] = DDR_CONFIG_PHY_DATA1_WR_DQS_SLAVE_RATIO;
DDR_PHY->DATA[1].WRLVL_INIT_RATIO[0] = DDR_CONFIG_PHY_DATA1_WRLVL_INIT_RATIO;
DDR_PHY->DATA[1].GATELVL_INIT_RATIO[0] = DDR_CONFIG_PHY_DATA1_GATELVL_INIT_RATIO;
DDR_PHY->DATA[1].FIFO_WE_SLAVE_RATIO[0] = DDR_CONFIG_PHY_DATA1_FIFO_WE_SLAVE_RATIO;
DDR_PHY->DATA[1].WR_DATA_SLAVE_RATIO[0] = DDR_CONFIG_PHY_DATA1_WR_DATA_SLAVE_RATIO;
DDR_PHY->DATA[1].DLL_LOCK_DIFF = DDR_CONFIG_PHY_DATA1_DLL_LOCK_DIFF;
//! Set control registers
CONTROL_MODULE->DDR_CMD0_IOCTRL = DDR_CONFIG_CMD_IOCTRL;
CONTROL_MODULE->DDR_CMD1_IOCTRL = DDR_CONFIG_CMD_IOCTRL;
CONTROL_MODULE->DDR_CMD2_IOCTRL = DDR_CONFIG_CMD_IOCTRL;
CONTROL_MODULE->DDR_DATA0_IOCTRL = DDR_CONFIG_DATA_IOCTRL;
CONTROL_MODULE->DDR_DATA1_IOCTRL = DDR_CONFIG_DATA_IOCTRL;
CONTROL_MODULE->DDR_IO_CTRL &= DDR_CONFIG_IOCTRL;
CONTROL_MODULE->DDR_CKE_CTRL |= DDR_CONFIG_CKE_CTRL;
//! Set memory interface control registers
EMIF0->DDR_PHY_CTRL_1 = DDR_CONFIG_PHY_CTRL_1;
EMIF0->DDR_PHY_CTRL_1_SHDW = DDR_CONFIG_PHY_CTRL_1;
EMIF0->DDR_PHY_CTRL_2 = DDR_CONFIG_PHY_CTRL_2;
//! Set memory interface timing registers
EMIF0->SDRAM_TIM_1 = DDR_CONFIG_SD_TIM_1;
EMIF0->SDRAM_TIM_1_SHDW = DDR_CONFIG_SD_TIM_1;
EMIF0->SDRAM_TIM_2 = DDR_CONFIG_SD_TIM_2;
EMIF0->SDRAM_TIM_2_SHDW = DDR_CONFIG_SD_TIM_2;
EMIF0->SDRAM_TIM_3 = DDR_CONFIG_SD_TIM_3;
EMIF0->SDRAM_TIM_3_SHDW = DDR_CONFIG_SD_TIM_3;
EMIF0->SDRAM_REF_CTRL = DDR_CONFIG_SD_REF_CTRL;
EMIF0->SDRAM_REF_CTRL_SHDW = DDR_CONFIG_SD_REF_CTRL;
EMIF0->SDRAM_CONFIG = DDR_CONFIG_SD_CONFIG;
//! Poll for DDR Phy ready indicator
while(!(EMIF0->STATUS & (1 << 2)));
//! Switch to User Mode
asm(" swi #0;");
问题中张贴的#define都是正确的。
答案 1 :(得分：0)
如果您从现有项目中使用此代码，则不太可能是序列问题。 SD-RAM的时序和信令参数是关键的，并且在不同器件之间有所不同，时序相关参数的实际寄存器值将取决于处理器的时钟速度。因此，除非您的DDR2设备与原始项目中使用的设备相同，并且您以相同的速度运行处理器，否则参数不太可能是正确的。
您需要将应用于内存控制器的设置与tour RAM部件数据表中提供的参数进行仔细匹配。这通常不是直截了当的，因为RAM供应商通常使用与处理器供应商使用的不同的术语来定义来自不同参考的参数。通常最简单的方法是使用两者中的时序图来选择兼容的参数。