Question

我为单独的wr / addr rd / addr内存做了一个vhdl代码即写入地址和数据，然后读取地址及其数据，但在模拟中，它不是很好，我想知道为什么？谢谢你的帮助

library ieee;
use ieee.std_logic_1164.all;
entity wr_rd_ram is
port(
    clk      : in  std_logic;
    we       : in  std_logic;
    wr_data  : in  std_logic_vector(7 downto 0);
    wr_addr  : in  integer range 0 to 255;
    rd_addr  : in  integer range 0 to 255; 
    rd_data  : out std_logic_vector(7 downto 0)
     );
   end entity;
  architecture rtl of wr_rd_ram is
 type mem is array(255 downto 0) of std_logic_vector(7 downto 0);
 signal ram : mem;
   begin
     process(clk)
  begin
      if(rising_edge(clk)) then
      if(we = '1') then
      ram(wr_addr) <= wr_data;
   end if;
  if (we= '0') then
    rd_data <= ram(rd_addr);
  end if;
 end if;
 end process;
 end  rtl ;

Answer 1

编写一个简单的测试平台：

library ieee;
use ieee.std_logic_1164.all;

entity tb_ram is
end entity;

architecture foo of tb_ram is
    signal clk:     std_logic := '0';
    signal we:      std_logic := '0';
    signal wr_data: std_logic_vector (7 downto 0):= x"42";
    signal wr_addr: integer range 0 to 255 := 0;
    signal rd_addr: integer range 0 to 255 := 0;
    signal rd_data: std_logic_vector ( 7 downto 0);
begin

CLOCK:
    process
    begin 
    wait for 10 ns;
    clk <= not clk;
    if Now > 130 ns then
        wait;
    end if;
    end process;

DUT:
    entity work.wr_rd_ram
        port map (
            clk => clk,
            we => we,
            wr_data => wr_data,
            wr_addr => wr_addr,
            rd_addr => rd_addr,
            rd_data => rd_data
        );

STIMULUS:
    process
    begin
        wait for 20 ns;
        we <= '1';
        wr_data <= x"de";
        wait for 20 ns;
        we <= '0';
        wait for 20 ns;
        wr_addr <= 1;
        wr_data <= x"ad";
        we <= '1';
        wait for 20 ns;
        we <= '0';
        wait for 20 ns;
        rd_addr <= 1;
        wait for 20 ns;
        wait;

    end process

end architecture;

分析，详细说明和运行给出：

当我们=＆＃39; 0＆＃39;你可以看到输出有一个时钟延迟。在rd_data端口上。

虽然这两个端口看起来很奇怪，但似乎无法工作。

什么不正确？任何预期的不同行为似乎都是您想要的和您指定的行为之间的差异。

有一点需要注意。当使用标量算法生成wr_addr或rd_addr时，您可以生成一个需要处理的超出范围的结果。＆＃34; +＆＃34;整数运算符不管理位[＆＃39;

当你将其中一个指针推到256时，你应该将它设置为0，模拟翻转。否则，您将收到超出范围的错误消息。

Answer 2

这个设计只是工作，但是当我将它用于另一个顶级设计时，它似乎在合成和模拟中工作，它没有模拟所有输入数据，即当我使用run all模拟所有结果时它重复我使用ise 9.2i程序设计的目的是给我数据输入之间的距离

data1,data2( (1, 2, 3, 4, 5), (5, 4, 3, 2, 1) ); distances  --> (4, 2, 0, 2, 4)
data1,data2( (1, 2, 3, 4), (4, 3, 2, 1) );           distances --> (3, 1, 1, 3)
data1,data2( (1, 2, 3), (1, 2, 3) );                   distances  --> (0, 0, 0)

，顶级设计水平是

library ieee;
use ieee.std_logic_1164.all;

entity test is
  port(
    rst      : in  std_logic;
    clk      : in  std_logic;
    we       : in  std_logic;
    wr_data1 : in  std_logic_vector(7 downto 0);
    wr_data2 : in  std_logic_vector(7 downto 0);
    wr_addr  : in  integer range 0 to 255;
    distance : out integer range 0 to 255;
    vout     : out std_logic;
    no_match : out std_logic
     );
   end entity;

   architecture rtl of test is

   signal rd_data1 : std_logic_vector(7 downto 0);
  signal rd_data2 : std_logic_vector(7 downto 0);
  signal rd_addr1 : integer range 0 to 255 := 0;
      signal rd_addr2 : integer range 0 to 255 := 0;
      signal d        : integer range 0 to 255 := 0;
       type states is (s0,s1,s2);
       signal state: states;

        component wr_rd_ram
      port(
    clk      : in  std_logic;
    we       : in  std_logic;
    wr_data  : in  std_logic_vector(7 downto 0);
    wr_addr  : in  integer range 0 to 255;
    rd_addr  : in  integer range 0 to 255; 
    rd_data  : out std_logic_vector(7 downto 0)
     );
       end component;

    begin

     ram1:entity work.wr_rd_ram
           port map(
    clk      => clk,
    we       => we,
    wr_data  => wr_data1,
    wr_addr  => wr_addr,
    rd_addr  => rd_addr1, 
    rd_data  => rd_data1
     );

 ram2:entity work.wr_rd_ram
  port map(
    clk      => clk,
    we       => we,
    wr_data  => wr_data2,
    wr_addr  => wr_addr,
    rd_addr  => rd_addr2, 
    rd_data  => rd_data2
     );
  process(rst,clk)
    begin
     if rst = '1' then 

rd_addr1 <= 0;
rd_addr2 <= 0;

state <= s0;
vout <= '0';
no_match <= '0';
distance <= 0;
  elsif rising_edge(clk) then
      if we  = '0' then
        vout <= '0';
       no_match <= '0';
      state <= s2;
        case state is
  when s0 =>
    rd_addr2 <= rd_addr2 + 1;
    if rd_data1 = rd_data2 then
       vout <= '1';
       d <= abs (rd_addr1-rd_addr2);

          state <= s1;
    elsif rd_addr2 = 255 then
       rd_addr2 <= 0;
       state <= s2;
    end if;

  when s1 =>
    rd_addr1 <= rd_addr1 + 1;

    rd_addr2 <= 0;
    state <= s0;

  when s2 =>
     no_match <= '1';
     state <= s0;

  when others => null;

 end case;
 end if;
 end if;
 distance <= d;
 end process;

   end rtl;

代码中没有模拟和运行输入1和输入2之间的所有比较有什么问题，我没有用测试台代码模拟我使用测试台波形

我的vhdl代码有什么问题？

2 个答案: