改变三角波形verilog的频率

Question

所以我已经得到了我的三角形波形，现在我想改变它的频率，但是我遇到错误，我不知道实际问题是什么。

module sxoc(clk,res,out1,freq,count);
input  clk,res;
input [0:7]freq;
output [0:7]count;
output [0:7]out1;
reg [0:7]out1;
always @(posedge clk)
begin
    if (res)
    begin
        out1=8'b00000000;
        count=8'b00000000;
    end
    else
        count =count + 1;
        if (count == freq)
            if(out1<=256)
            begin
                out1=out1 + 1;
                count = 0;
            end
end
endmodule
module atam_test;
reg clk,res;
reg [0:7]freq;
wire [0:7]count;
wire [0:7]out1;
sxoc sxoc1(clk,res,out1,freq,count);
always #2 clk=~clk;
initial 
begin
clk=0;res=1;freq=8'b00000011;
#5 res=0;
end
initial #5000 $finish;
endmodule

Answer 1

程序分配（在always区块中）只能对reg进行。变化：

output [0:7]count;

为：

output reg [0:7]count;