Question

错误：HDLCompiler：69 - “D：/ xilinx program / and2 / kj.vhd”第82行：未声明。

错误：HDLC编译器：580 - “D：/ xilinx program / and2 / kj.vhd”第85行：标签不匹配;预期的行为

错误：HDLCompiler：854 - “D：/ xilinx program / and2 / kj.vhd”第38行：由于先前的错误而忽略了单位。

library ieee;
use ieee.std_logic_1164.all;

entity kj is
end kj;

architecture behavior of kj is

-- Component Declaration for the Unit Under Test (UUT)

  component and2
    port(
      a : in  std_logic;
      b : in  std_logic;
      c : out std_logic
      );
  end component;

--Inputs
  signal a : std_logic := '0';
  signal b : std_logic := '0';
--signal clk : std_logic :='0';
--Outputs
  signal c : std_logic;
  -- No clocks detected in port list. Replace <clock> below with
  -- appropriate port name

begin

-- Instantiate the Unit Under Test (UUT)
  uut : and2 port map (
    a => a,
    b => b,
    c => c
    );

  -- Clock process definitions
  -- Stimulus process
  a <= '0', '1' after 50 ns, '0' after 80 ns;
  b <= '0', '1' after 30 ns, '0' after 120 ns;
  process
  begin
    wait for 60 ns;
    assert(c = '1')
      report "output of and gate is incorrect"
      severity node;
  end process;
end kj;

Answer 1

要编译要纠正的两个问题：

第46行：“节点;” =＆GT; “注意，”
第48行：“结束kj;” =＆GT; “结束行为;”

请更正我的代码这是nand gate的测试平台，我有一些错误吗？请帮帮我

1 个答案: