我有一个与ADC值连续平均有关的问题。我使用的方法是对示例256个样本进行连续平均。我在GUI上收到的''adc_a_out''值（如下面的代码所示）递增缓慢。例如，如果我期望值100mA，我的GUI显示4mA，8mA，15mA ......，然后最终在2分钟后我得到稳定的100mA值。我希望从'adc_a_out'直接在我的GUI上看到100mA，而不是增量值，并在一段时间后稳定下来。另一个问题是，我能否以某种方式快速完成此过程，以便我不必等待3分钟从adc_a_out接收稳定的100 mA。下面数字设计中的时钟'clk'是20 MHz。用于在FPGA板上接收ADC值的时钟为15 KHz。
--adc_top_file.vhd
entity adc_block_1 is
port (
clk : in std_logic;
reset : in std_logic;
data_in : in std_logic_vector (31 downto 0);
req : in std_logic;
adc_a_1 : inout std_logic_vector (11 downto 0);
adc_b_1 : inout std_logic_vector (11 downto 0);
slv_value1 : out std_logic_vector (11 downto 0);
slv_value2 : out std_logic_vector (11 downto 0);
);
end adc_block_1;
architecture adc_top_block of adc_block_1 is
component adc is
port (
clk : in std_logic;
reset : in std_logic;
data_in : in std_logic_vector (31 downto 0);
req : in std_logic;
adc_a_1 : inout std_logic_vector (11 downto 0);
adc_b_1 : inout std_logic_vector (11 downto 0);
adc_a_1_temp: out signed(11 downto 0);
adc_b_1_temp: out signed(11 downto 0);
slv_value1 : out std_logic_vector (11 downto 0);
slv_value2 : out std_logic_vector (11 downto 0);
);
end component;
component use_moving_average is
port (
clock: in std_logic;
reset: in std_logic;
channel_1_sample: in signed(11 downto 0);
channel_2_sample: in signed(11 downto 0);
channel_1_average: inout signed(11 downto 0);
channel_2_average: inout signed(11 downto 0);
slv_value1 : out std_logic_vector (11 downto 0);
slv_value2 : out std_logic_vector (11 downto 0)
);
end component;
signal adc_a_1_temp : std_logic_vector(11 downto 0);
signal adc_b_1_temp : std_logic_vector(11 downto 0);
signal adc_a_1_out : std_logic_vector(11 downto 0);
signal adc_b_1_out : std_logic_vector(11 downto 0);
begin
inst_adc : adc
port map (
clk => clk,
reset => reset,
req => adc_req,
adc_a_1 => adc_a_1_temp,
adc_b_1 => adc_b_1_temp,
adc_a_1_temp => adc_a_1_temp,
adc_b_1_temp => adc_b_1_temp
);
inst_moving_average : use_moving_average
port map (
clock => clk,
reset => reset,
channel_1_sample => adc_a_1_temp,
channel_2_sample => adc_b_1_temp,
channel_1_average => adc_a_1_out,
channel_2_average => adc_b_1_out,
slv_value1 => slv_value1,
slv_value2 => slv_value2
);
- adc.vhd文件如下：
data_in : in std_logic_vector (31 downto 0);
adc_a_1 : inout std_logic_vector (11 downto 0);
adc_b_1 : inout std_logic_vector (11 downto 0);
adc_a_1_temp: out signed(11 downto 0);
adc_b_1_temp: out signed(11 downto 0);
load : out std_logic;
process (clk, reset)
begin
if (reset = '1') then
state<=idle;
adc_out1=0;
adc_out2 <= 0;
elsif(rising_edge(clk)) then
case state is
when idle =>
if req='1' then
state= out_1;
end if;
when out_1 =>
if done='1' then
data_out <= addr0 & bits;
adc_a_1 <= data_in(11 downto 0);
adc_a_1_temp <= signed(adc_a_1);
state <= out_2;
endif;
when out_2 =>
if done='1' then
adc_b_1 <= data_in(11 downto 0);
adc_b_1_temp <= signed(adc_b_1);
state <= done_st;
when done_st =>
ack <='1';
--load <='1';
state <= idle;
when others =>
state <= idle;
end case;
end if;
end process;
load: process (clk, reset)
begin
if (reset = '1') then
load <= '0';
elsif (rising_edge(clk)) then
max_cnt <= 5000000;
load <= '0';
else
max_cnt <= max_cnt -1;
load <= '1';
end if;
end process load;
您的代码修改如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity use_moving_average is
port (
clock: in std_logic;
reset: in std_logic;
channel_1_sample: in signed(11 downto 0);
channel_2_sample: in signed(11 downto 0);
channel_1_average: inout signed(11 downto 0);
channel_2_average: inout signed(11 downto 0);
slv_value1 : out std_logic_vector (11 downto 0);
slv_value2 : out std_logic_vector (11 downto 0)
);
end;
architecture rtl of use_moving_average is
signal average_1, average_2: integer;
begin
channel_1: entity work.moving_average
port map(
sample => to_integer(channel_1_sample),
average => average_1,
clock => clock,
reset => reset
);
channel_2: entity work.moving_average
port map(
sample => channel_2_sample,
average => average_2,
clock => clock,
reset => reset
);
channel_1_average <= to_signed(average_1, 12);
slv_value1 <= std_logic_vector(channel_1_average);
channel_2_average <= to_signed(average_2, 12);
slv_value2 <= std_logic_vector(channel_2_average);
end;
我在GUI上查看的最终输出是'slv_value1'和'slv_value2'
谢谢！
答案 0 :(得分：2)
如何：在重置时（或在任何其他时间，如果需要），将data_in值分配给stage数组中的所有元素。这应该立即将您的平均值设置为当前值：
process (clk, reset)
begin
if (reset = '1') then
out_val <= 0;
stage <= (others => data_in(11 downto 0));
sum <= resize(255 * signed(data_in(11 downto 0)), sum'length);
elsif rising_edge(clk) then
...
下面的示例显示了移动平均值计算器的完整代码。我的建议是你学习它直到你明白它。然后，尝试在您的设计中使用它。最后，只有在基本电路工作后，才能更改它以满足您的设计约束（数据宽度，样本数，整数范围，signed与integer的使用等。 ）
library ieee;
use ieee.std_logic_1164.all;
entity moving_average is
generic(
SAMPLES_COUNT: integer := 256
);
port (
sample: in integer;
average: out integer;
clock: in std_logic;
reset: in std_logic
);
end;
architecture rtl of moving_average is
signal samples_fifo: integer_vector(1 to SAMPLES_COUNT);
signal sum: integer;
begin
process (clock, reset) begin
if reset then
samples_fifo <= (others => sample);
sum <= SAMPLES_COUNT * sample;
elsif rising_edge(clock) then
samples_fifo <= sample & samples_fifo(1 to SAMPLES_COUNT-1);
sum <= sum + sample - samples_fifo(SAMPLES_COUNT);
end if;
end process;
average <= sum / SAMPLES_COUNT;
end;
最后，如果您想使用上面的代码为两个不同的信号保留两个单独的平均值，只需实例化两次平均实体：
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity use_moving_average is
port (
clock: in std_logic;
reset: in std_logic;
channel_1_sample: in signed(11 downto 0);
channel_2_sample: in signed(11 downto 0);
channel_1_average: out signed(11 downto 0);
channel_2_average: out signed(11 downto 0)
);
end;
architecture rtl of use_moving_average is
signal average_1, average_2: integer;
begin
channel_1: entity work.moving_average
port map(
sample => to_integer(channel_1_sample),
average => average_1,
clock => clock,
reset => reset
);
channel_2: entity work.moving_average
port map(
sample => channel_2_sample,
average => average_2,
clock => clock,
reset => reset
);
channel_1_average <= to_signed(average_1, 12);
channel_2_average <= to_signed(average_2, 12);
end;
编辑：据我所知，您可能需要额外输入才能将当前平均值设置为当前输入值。在这种情况下，您可以使用load输入，如下所示：
library ieee;
use ieee.std_logic_1164.all;
entity moving_average is
generic(
SAMPLES_COUNT: integer := 256
);
port (
sample: in integer;
average: out integer;
clock: in std_logic;
reset: in std_logic;
load: in std_logic
);
end;
architecture rtl of moving_average is
signal samples_fifo: integer_vector(1 to SAMPLES_COUNT);
signal sum: integer;
begin
process (clock, reset) begin
if reset then
samples_fifo <= (others => sample);
sum <= SAMPLES_COUNT * sample;
elsif rising_edge(clock) then
if load then
samples_fifo <= (others => sample);
sum <= SAMPLES_COUNT * sample;
else
samples_fifo <= sample & samples_fifo(1 to SAMPLES_COUNT-1);
sum <= sum + sample - samples_fifo(SAMPLES_COUNT);
end if;
end if;
end process;
average <= sum / SAMPLES_COUNT;
end;