Question

我目前正在使用结构Verilog制作一个32位MIPS ALU，并希望模拟每个OP代码至少10次并计算不同输入的平均延迟。

我有一个测试平台，目前的功能如下（请记住，这是我的第一个verilog项目）

`include "alu_unit.v"
`timescale 1ns/1ns
/* ---------
OP CODES:
000 = AND
001 = OR
010 = ADD
110 = SUB
111 = SLT
-----------*/ 
module alu_tb;
reg[2:0] op;
reg signed [31:0] a,b;
wire[31:0] out,overflow;
wire zero;

fullALU testALU(a,b,op,cout,out,zero,overflow);

initial
begin
    $monitor($time,,"a=%d, b=%d, op=%b, out=%b, overflow=%b, zero=%b",a,b,op,out,overflow,zero );
    $display($time,,"a=%d, b=%d, op=%b, out=%b, overflow=%b, zero=%b",a,b,op,out,overflow,zero );
    #10 a=$random; b=$random; op=010; 
    #10 // Required
    $display($time,,"a=%d, b=%d, op=%b, out=%b, overflow=%b, zero=%b",a,b,op,out,overflow,zero );
end
endmodule

是否可以创建一个带有两个随机32位输入（A，B）和相应OP代码的函数，运行模拟直到电路输出完成（对于每个32位）并执行此操作，例如10次？然后，它将计算运行的10个电路所需的平均延迟。

我正在运行单位门延迟模型，因此每个门的延迟为1ns（尽管此处未显示结构代码）。

欢迎批评我的Verilog编码。

                   0 a=          x, b=          x, op=xxx, out=         z, overflow=zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz, zero=z
                   0 a=          x, b=          x, op=xxx, out=         z, overflow=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, zero=x
                   1 a=          x, b=          x, op=xxx, out=         X, overflow=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, zero=x
                  10 a=     214743, b=      12342, op=010, out=         X, overflow=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, zero=x
                  11 a=     214743, b=      12342, op=010, out=         x, overflow=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, zero=x
                  15 a=     214743, b=      12342, op=010, out=         x, overflow=0000000000000xxxxxxxxxxxxxxxxxx0, zero=x
                  16 a=     214743, b=      12342, op=010, out=         X, overflow=0000000000000xxxxxxxxxxxxxx11010, zero=0
                  17 a=     214743, b=      12342, op=010, out=         X, overflow=0000000000000xx0xxx0xx0xxxx11010, zero=0
                  18 a=     214743, b=      12342, op=010, out=         X, overflow=0000000000000xx0xxx0xx0xxx011010, zero=0
                  19 a=     214743, b=      12342, op=010, out=         X, overflow=0000000000000000xx00000xxx011010, zero=0
                  20 a=     214743, b=      12342, op=010, out=         X, overflow=0000000000000000xx00000xxx011010, zero=0
                  20 a=     214743, b=      12342, op=010, out=         X, overflow=0000000000000000xx00000xx0011010, zero=0
                  21 a=     214743, b=      12342, op=010, out=         X, overflow=00000000000000000000000xx0011010, zero=0
                  22 a=     214743, b=      12342, op=010, out=         X, overflow=00000000000000000000000100011010, zero=0
                  23 a=     214743, b=      12342, op=010, out=         X, overflow=00000000000000000000000100011010, zero=0
                  24 a=     214743, b=      12342, op=010, out=    227085, overflow=00000000000000000000000100011010, zero=0

结构Verilog模拟（计算平均延迟）

0 个答案: