Question

这里有一点来自我的verilog代码

reg [17:0]FilterCoeffRam[95:0]; // Filter Coefficients   
reg [17:0]CoeffRam01[0:5];  
reg [17:0]CoeffRam02[0:5];  
reg [17:0]CoeffRam03[0:5];  
reg [17:0]CoeffRam04[0:5];  
reg [17:0]CoeffRam05[0:5];  
reg [17:0]CoeffRam06[0:5];  
reg [17:0]CoeffRam07[0:5]; 
reg [17:0]CoeffRam08[0:5];  
reg [17:0]CoeffRam09[0:5];  
reg [17:0]CoeffRam10[0:5];  
reg [17:0]CoeffRam11[0:5];  
reg [17:0]CoeffRam12[0:5];  
reg [17:0]CoeffRam13[0:5];  
reg [17:0]CoeffRam14[0:5];  
reg [17:0]CoeffRam15[0:5];  
reg [17:0]CoeffRam16[0:5];  
integer k;

initial  
begin  
        $readmemh("FilterCoeff96.txt",FilterCoeffRam);  
        for(k=0; k<6; k=k+1)  
            begin  
           CoeffRam01[k]=FilterCoeffRam[k];  
            CoeffRam02[k]=FilterCoeffRam[k+6];  
            CoeffRam03[k]=FilterCoeffRam[k+12];  
            CoeffRam04[k]=FilterCoeffRam[k+18];  
            CoeffRam05[k]=FilterCoeffRam[k+24];  
            CoeffRam06[k]=FilterCoeffRam[k+30];  
            CoeffRam07[k]=FilterCoeffRam[k+36];  
            CoeffRam08[k]=FilterCoeffRam[k+42];  
            CoeffRam09[k]=FilterCoeffRam[k+48];  
            CoeffRam10[k]=FilterCoeffRam[k+54];  
            CoeffRam11[k]=FilterCoeffRam[k+60];  
            CoeffRam12[k]=FilterCoeffRam[k+66];  
            CoeffRam13[k]=FilterCoeffRam[k+72];  
            CoeffRam14[k]=FilterCoeffRam[k+78];  
            CoeffRam15[k]=FilterCoeffRam[k+84];  
            CoeffRam16[k]=FilterCoeffRam[k+90];  
         end  
    end

我正在从txt文件中读取96个18位十六进制值＆amp;将它们存储到FilterCoeffRam寄存器中然后我将这些系数平均分配到16个寄存器中。理想情况下，这16个6x18位寄存器应合成为ROM。但综合报告并未将这些列为ROM，而是列为寄存器。

WARNING:Xst:1780 - Signal <FilterCoeffRam> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1781 - Signal <CoeffRam16> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam15> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam14> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam13> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam12> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam11> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam10> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam09> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam08> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam07> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam06> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam05> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam04> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam03> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam02> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam01> is used but never assigned. Tied to default value.

我如何确保它们被推断为ROM＆amp;不是注册

Answer 1

我没有从你的报告中看到是什么让你认为他们是登记册。

您可能只想构建一个可以非常有效地合成的LUT（查找表），而不是物理ROM宏。

如果您一次只需要其中一个系数，则可能会对以下内容有所帮助：

always @* begin //Combinatorial block (no flip_flops)
   case( addr )
     0: coeff = 32'd23  ;
     1: coeff = 32'd43  ;
     2: coeff = 32'd255 ;
     // etc ...
end

Answer 2

您的第一个警告是告诉您readmemh无效。尝试将此缩减为最简单的形式，根据XST文档：

reg [17:0] FilterCoeffRam [95:0];
initial begin
  $readmemh("coeffs.txt", FilterCoeffRam, 95, 0);
end

（begin / end显然也是多余的）。接下来，您可能必须摆脱for循环; XST可能无法与readmemh一起展开。你有效地要求XST将CoeffRam0x实例视为ROM，我认为它可能会被混淆。无论如何，它没有做任何有用的事情 - 尝试在寻址逻辑中处理这个问题。第三，不要指望这些东西进入特定的“ROM” - 例如，它将以V6中的27个LUT进入（即27个迷你ROM）。

Answer 3

您应该使用始终块和时钟，否则将无法推断RAM。在推断RAM时，综合工具可能很挑剔，因此请确保遵循供应商文档中给出的确切格式。查看XST用户指南，了解您使用的任何版本：http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/xst.pdf

如何在verilog中将寄存器块合成为ROM

3 个答案: