以下是JK FlipFlop的代码: -
entity jkasync is
Port ( j : in std_logic;
k : in std_logic;
r : in std_logic;
clk : in std_logic;
q : inout std_logic);
end jkasync;
architecture Behavioral of jkasync is
signal s: std_logic_vector(1 downto 0);
s <= j&k;
begin
process (j,k,r,clk)
begin
if (r='1') then
q<='0';
elsif (falling_edge(clk)) then
case s is
when "00" =>q<=q;
when "01" =>q<='0';
when "10" =>q<='1';
when "11" =>q<= not q;
when others =>q<='0';
end case;
end if;
end process;
end Behavioral;
我收到以下错误: -
第21行。解析错误,意外IDENTIFIER
第21行是s<=j&k;
所以请帮我纠正这段代码的语法,请告诉我这里有什么问题。
谢谢。
答案 0 :(得分:0)
知道了。
在架构体中初始化一个新信号,但该值在流程体内定义。
在行程中移动第21行。
正确代码: -
architecture Behavioral of jkasync is
signal s: std_logic_vector(1 downto 0);
begin
s <= j&k;
process (j,k,r,clk)
begin
if (r='1') then
q<='0';
elsif (falling_edge(clk)) then
case s is
when "00" =>q<=q;
when "01" =>q<='0';
when "10" =>q<='1';
when "11" =>q<= not q;
when others =>q<='0';
end case;
end if;
end process;
end Behavioral;