Question

我尝试了使用VHDL设计可变位计数器（像ring或Johnson这样的任何计数器）的不同方法，但都是徒劳的。

任何人都可以帮助我克服这个问题吗？

Answer 1

在VHDL中：

您需要首先描述计数器的引脚：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter
port (
  clk    : in std_ulogic;
  resetn : in std_ulogic;
  count  : out unsigned
);

然后描述它的行为：

architecture behaviour of counter is

begin
  process(clk) -- run this process whenever CLK changes
  begin
    if rising_edge(clk) then -- only on the rising edges, run the code
      if reset = '1' then    
        count <= (others => '0'); -- set count to all bits 0
      else
        count <= count + 1; -- you'll need VHDL-2008 switched on to do this as it is reading an output signal
      end if;
    end if;
  end process;
end architecture;

当您使用此计数器时，计数信号将从更高级别附加的信号继承正确的位数。

Answer 2

Johnson计数器as per the wikipedia schematic只是一个移位寄存器，下一个LSB是反向MSB。

module johnson_counter #(
  parameter WIDTH = 4
) (
  input                  clk,
  input                  rst_n,
  output reg [WIDTH-1:0] state
);
always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    state <= {WIDTH{1'b0}}; //Replication to extend 1'b0
  end
  else begin
    //Shift Left 1, bit LSB becomes inverted MSB
    state <= {state[WIDTH-2:0], ~state[WIDTH-1]}; //Concatination
  end
endmodule

如何使用VHDL或Verilog设计可变位（m位）计数器？

2 个答案: