Question

我的第一个verilog作业将在几天后到期，无论出于何种原因，这些概念都在逃避我。我不认为我在考虑并行性和硬件等方面。

我的问题是，我必须使用and wire一起使用几个开关和按钮，并打开7个数组中的3个LED。我很确定我知道如何进行计算逻辑，但我无法弄清楚如何使用assign和wire来正确打开所有3个LED，而无需编写3条独立的线路。感觉不对：

assign Led[0] = output;
assign Led[1] = output;
assign Led[2] = output;

另外，这很奇怪，因为电路板上有7个LED，我正在选择LED 0,2,4。

有人可以告诉我这应该如何运用正确的方式吗？我们没有教科书，我一直在网上阅读基础知识，但我似乎无法弄清楚这是如何工作的。谢谢！

编辑：这是我当前的代码，但我收到错误，说什么都没有“驱动”。是什么给了什么？

module Lab2_1(input [5:0] sw, input btns, output [7:0] Led );

    wire [2:0] leds; 
    wand out; 

    assign leds = {Led[0], Led[2], Led[4]};

    and U1   (out, sw[0], sw[1]);
    and U2   (out,~sw[2],~sw[3]);
    xor U3   (out,sw[4],sw[5]);
    assign   out = btns;
    assign leds[2:0] = {3{out}};

endmodule

错误：

ERROR:PhysDesignRules:368 - The signal <Led<3>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal <Led<4>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal <Led<5>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal <Led<6>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal <Led<7>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal <Led<0>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal <Led<1>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal <Led<2>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:10 - The network <Led<3>_OBUF> is completely unrouted.
ERROR:PhysDesignRules:10 - The network <Led<4>_OBUF> is completely unrouted.
ERROR:PhysDesignRules:10 - The network <Led<5>_OBUF> is completely unrouted.
ERROR:PhysDesignRules:10 - The network <Led<6>_OBUF> is completely unrouted.
ERROR:PhysDesignRules:10 - The network <Led<7>_OBUF> is completely unrouted.
ERROR:PhysDesignRules:10 - The network <Led<0>_OBUF> is completely unrouted.
ERROR:PhysDesignRules:10 - The network <Led<1>_OBUF> is completely unrouted.
ERROR:PhysDesignRules:10 - The network <Led<2>_OBUF> is completely unrouted.
ERROR:Bitgen:25 - DRC detected 16 errors and 0 warnings.  Please see the
   previously displayed individual error or warning messages for more details.

Answer 1

你已经看起来完全没问题，但是如果你想在一行中做到这一点，你可以使用连接和/或复制操作符来分配多个Led位。这两个语句都等同于您的代码示例：

assign Led[2:0] = {output, output, output};

或

assign Led[2:0] = {3{output}};

我不知道这些是否比你现有的更好或更合适，只是写下它们来展示一些可能的例子。

===编辑===

您收到错误是因为您没有驾驶任何Led位。

向后看：assign leds = {Led[0], Led[2], Led[4]};
Led是模块的输出，因此它应该被赋值，意味着它应该在等于的左侧，所以我猜这应该看起来像{{1 }}
您的模块有一个8位Led输出，但您只需分配3位。您应该将其他5位分配给常数1或0。

基本的Verilog概念

1 个答案: