我是一名学生，刚刚开始学习vhdl。所以我需要有人指出我正确的方向。这就是我到目前为止所做的：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX81 IS
PORT(
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
Z : OUT STD_LOGIC);
END MUX81;
ARCHITECTURE struc OF MUX81 IS
SIGNAL Z1,Z2:STD_LOGIC;
COMPONENT mux41 is
PORT(A,B,C,D,S0,S1:IN STD_LOGIC;Q:OUT STD_LOGIC);
END COMPONENT;
COMPONENT mux21 is
PORT(M,N,S2:IN STD_LOGIC;O:OUT STD_LOGIC);
END COMPONENT;
for M1,M2:mux41
use entity work.mux41(struc1);
for M3:mux21
use entity work.mux21(arc);
signal Z1,Z2: std_logic;
BEGIN
M1 : mux41 PORT MAP(A(0),A(1),A(2),A(3),S(0),S(1),Z1);
M2 : mux41 PORT MAP(A(4),A(5),A(6),A(7),S(0),S(1),Z2);
M3 : mux21 PORT MAP(Z1,Z2,S(2),O);
END struc;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux41 IS
PORT(
A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Z : OUT STD_LOGIC);
END mux41;
ARCHITECTURE struc1 OF mux41 IS
component and3 is
(a,b,c : in std_logic;d : out std_logic);
end component;
component or4 is
(a,b,c,d : in std_logic;e : out std_logic);
end component;
for A1,A2,A3,A4:and3
use entity work.and3(arc3);
for OR1:or4
use entity work.or4(arc2);
signal s1,s2,s3,s4 : std_logic;
begin
A1 : and3 port map(A(0),not S(0),not S(1),s1);
A2 : and3 port map(A(1),not S(0),S(1),s2);
A3 : and3 port map(A(2),S(0),not S(1),s3);
A4 : and3 port map(A(3),S(0),S(1),s4);
OR1 : or4 port map (s1,s2,s3,s4,Z);
end struc1;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity mux21 is
port(a,b,s : in bit;
c : out bit);
end mux21;
architecture arc of mux21 is
signal O1,O2:std_logic;
component and3 is
(a,b,c : in std_logic;d : out std_logic);
end component;
component or2 is
(a,b : in std_logic;c : out std_logic);
end component;
for A5,A6:and3
use entity work.and3(arc3);
for O1:or2
use entity work.or2(arc1);
begin
A5 : and3 port map(Z1,not S2,O1);
A6 : and3 port map(Z2,S2,O2);
O1 : or2 port map(O1,O2,O);
end arc;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity or2 is
port(a,b : in bit;
c : out bit);
end or2;
architecture arc1 of or2 is
begin
c<=a or b;
end arc1;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity or4 is
port(a,b,c,d : in bit;
e : out bit);
end or4;
architecture arc2 of or4 is
begin
e<=a or b or c or d;
end arc2;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity and3 is
port(a,b,c : in bit;
d : out bit);
end and3;
architecture arc3 of and3 is
begin
d<=a and b and c;
end arc3;
错误日志：
# Compile...
# File: c:\Users\Divyanshu\Downloads\HDL\div\mux\src\try.vhd
# Compile Entity "MUX81"
# Entity `MUX81' has been skipped - no difference detected.
# Compile Architecture "struc" of Entity "MUX81"
# Error: ELAB1_0021: try.vhd : (18, 1): Types do not match for port "A".
# Error: ELAB1_0011: try.vhd : (18, 0): Port "S" is on entity "mux41" but not on the component declaration.
# Error: ELAB1_0030: try.vhd : (18, 0): Port "B" is on component "mux41" but not on the entity "mux41".
# Error: ELAB1_0030: try.vhd : (18, 0): Port "C" is on component "mux41" but not on the entity "mux41".
# Error: ELAB1_0030: try.vhd : (18, 0): Port "D" is on component "mux41" but not on the entity "mux41".
# Error: ELAB1_0030: try.vhd : (18, 0): Port "S0" is on component "mux41" but not on the entity "mux41".
# Error: ELAB1_0030: try.vhd : (18, 0): Port "S1" is on component "mux41" but not on the entity "mux41".
# Error: ELAB1_0030: try.vhd : (18, 0): Port "Q" is on component "mux41" but not on the entity "mux41".
# Error: COMP96_0122: try.vhd : (21, 1): Symbol "Z1" has already been declared in this region.
# Error: COMP96_0122: try.vhd : (21, 1): Symbol "Z2" has already been declared in this region.
# Error: COMP96_0078: try.vhd : (25, 32): Unknown identifier "O".
# Error: COMP96_0133: try.vhd : (25, 32): Cannot find object declaration.
# Error: COMP96_0104: try.vhd : (25, 32): Undefined type of expression.
# Compile Entity "mux41"
# Entity `mux41' has been skipped - no difference detected.
# Compile Architecture "struc1" of Entity "mux41"
# Error: COMP96_0019: try.vhd : (39, 1): Keyword "end" expected.
# Error: COMP96_0018: try.vhd : (40, 14): Identifier expected.
# Error: COMP96_0019: try.vhd : (42, 1): Keyword "end" expected.
# Error: COMP96_0018: try.vhd : (43, 14): Identifier expected.
# Compile Entity "mux21"
# Entity `mux21' has been skipped - no difference detected.
# Compile Architecture "arc" of Entity "mux21"
# Error: COMP96_0019: try.vhd : (67, 1): Keyword "end" expected.
# Error: COMP96_0018: try.vhd : (68, 14): Identifier expected.
# Error: COMP96_0019: try.vhd : (70, 1): Keyword "end" expected.
# Error: COMP96_0018: try.vhd : (71, 14): Identifier expected.
# Compile Entity "or2"
# Entity `or2' has been skipped - no difference detected.
# Compile Architecture "arc1" of Entity "or2"
# Compile Entity "or4"
# Entity `or4' has been skipped - no difference detected.
# Compile Architecture "arc2" of Entity "or4"
# Compile Entity "and3"
# Entity `and3' has been skipped - no difference detected.
# Compile Architecture "arc3" of Entity "and3"
# Compile failure 21 Errors 0 Warnings Analysis time : 0.4 [s]
我知道一些错误是非常基本的，但这是我自己在VHDL上的第一个项目。 Thanx提前。
答案 0 :(得分：1)
你有一个组件声明
COMPONENT mux41 is
PORT(A,B,C,D,S0,S1:IN STD_LOGIC;Q:OUT STD_LOGIC);
和实体声明
ENTITY mux41 IS
PORT(
A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Z : OUT STD_LOGIC);
END mux41;
这些是非常不同的。错误消息会告诉您究竟出了什么问题。
Error: ELAB1_0021: try.vhd : (18, 1): Types do not match for port "A".
Error: ELAB1_0011: try.vhd : (18, 0): Port "S" is on entity "mux41" but not on the component declaration.
Error: ELAB1_0030: try.vhd : (18, 0): Port "B" is on component "mux41" but not on the entity "mux41".
Error: ELAB1_0030: try.vhd : (18, 0): Port "C" is on component "mux41" but not on the entity "mux41".`
确实，端口A是一个std_logic，另一个是std_logic_vector：如消息所示，这些不匹配。并且实体具有端口“S”而组件没有。等等...
修复它们可能涉及编写与组件匹配的新实体，或编辑组件声明和端口映射以匹配您已有的实体。
正如Morten所说，捕捉模拟中的基本错误......如果你无法访问Modelsim，免费的Xilinx工具包含一个不错的模拟器（Isim）或者有开源工具GHDL。 / p>
答案 1 :(得分：0)
正如MortenZdk所说，使用像ModelSim这样的模拟器来学习VHDL语法更好。您可以编译单个VHDL文件而不是整个项目，并运行模拟器来验证它。 ModelSim很容易用于其出色的在线教程：）。