Question

我在用VHDL设计存储器电路时遇到问题。我试图找出以下提示的灵魂：

使用结构VHDL方法在Xilinx工具中创建NAND基本单元。在两个与非门上增加1ns的门延迟（上升和下降转换）。标记输入S和R以及输出Q和QN。创建一个VHDL测试平台来模拟电路，按照下面的规定驱动输入。

在模拟开始时取消断言两个输入。在100ns，资产S.在200ns，取消断言S.在300ns，断言R.在400ns，取消断言R.在500ns，断言两个输入。在600ns时，取消断言两个输入。在700ns时，断言两个输入。

未定义的输出
设定操作
重置操作
存储在内存中的'0'
存储在内存中的“1”
Q和QN输出均被驱动为相同值的状态
亚稳态

如果我只能得到代码看起来像的基本示例，我也可以设计一个NOR电路（这是我想要解决的实际问题），但NAND示例就足够了。

我尝试将此模型用于结构代码

 import std_logic from the IEEE library
    library ieee;
    use ieee.std_logic_1164.all;

    --ENTITY DECLARATION: name, inputs, outputs
    entity nandGate is
       port( A, B : in std_logic;
                F : out std_logic);
    end nandGate;

    --FUNCTIONAL DESCRIPTION: how the NAND Gate works
    architecture func of nandGate is 
    begin
       F <= A nand B;
    end func;

and this model for the test bench 



 architecture tb of nandGate_tb is
       --pass nandGate entity to the testbench as component 
       component nandGate is
       port( A, B : in std_logic;
                F : out std_logic);
       end component;

       signal  inA, inB, outF : std_logic;
    begin
       --map the testbench signals to the ports of the nandGate
       mapping: nandGate port map(inA, inB, outF);

       process
          --variable to track errors
          variable errCnt : integer := 0;
       begin
          --TEST 1
          inA <= '0';
          inB <= '0';
          wait for 15 ns;
          assert(outF = '1')  report "Error 1" severity error;
          if(outF /= '1') then
             errCnt := errCnt + 1;
          end if;

          --TEST 2
          inA <= '0';
          inB <= '1';
          wait for 15 ns;
          assert(outF = '1')  report "Error 2" severity error;
          if(outF /= '1') then
             errCnt := errCnt + 1;
          end if;

          --TEST 3
          inA <= '1';
          inB <= '1';
          wait for 15 ns;
          assert(outF = '0')  report "Error 3" severity error;
          if(outF /= '0') then
             errCnt := errCnt + 1;
          end if;

          -------------- SUMMARY -------------
          if(errCnt = 0) then
             assert false report "Good!"  severity note;
          else
             assert true report "Error!"  severity error;
          end if;

       end process;
    end tb;

Answer 1

问题是要求您从交叉耦合的NAND门对中创建SR锁存器（在指令中称为NAND基本单元）。所提到的延迟将在NAND门的功能描述的逻辑方程中。

以下是由两个与非门构成的SR锁存器的结构VHDL模型：

entity nandCell is
   port( S, R  : in std_logic; --S and R are active low
         Q, QN : out std_logic);
end nandCell;

architecture structural of nandCell is 
   --NAND gate component declaration
   signal Qint, QNint : std_logic; --these internal signals are required to be able to read the "outputs"
begin
   n1 : nandGate port map(S, QNint, Qint);
   n2 : nandGate port map(R, Qint, QNint);
   Q <= Qint;
   QN <= QNint;
end structural;

NAND基本单元使用结构vhdl

1 个答案: