Question

我想知道是否有办法在VHDL中使用size参数定义类型。 e.g。

type count_vector(size: Natural) is unsigned (size-1 downto 0);

然后再做类似

的事情

variable int : count_vector(32) := (others => '0');
variable nibble : count_vector(4) := (others => '0');

基本上，有没有办法定义“类似数组”类型，还是语法不允许？

我目前正在尝试使用泛型来实现可重用性，但我希望能够最大限度地利用泛型类型（即：Is it possible to write type-generic entities in VHDL?）。

提前致谢！

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity foo is
     generic (
        constant INT_LEFT:    natural := 32;
        constant NIB_LEFT:    natural := 4
     );
     -- note entity declarative items are forward looking only
     -- a port declaration requires a type or subtype declared in a package
     -- you can also use a package for any constants

     -- a type or subtype can be declared as an entity declarative item here:
--     subtype int_size is unsigned(INT_LEFT downto 0);
--     subtype nib_size is unsigned(NIB_LEFT downto 0);
end entity;

architecture fum of foo is
    -- or as an architecture declarative item here:
    subtype int_size is unsigned(INT_LEFT downto 0);
    subtype nib_size is unsigned(NIB_LEFT downto 0);   

begin
USAGE:
    process 
        variable int:  int_size := (others => '0');
        variable nibble: nib_size := (others =>'0');
    begin
        int := int + 3;
        -- the function "+" is L: UNSIGNED, R: NATURAL
        --  int_size and nibble_size are subtypes of UNSIGNED
        Report integer'IMAGE(TO_INTEGER(int));
        -- ditto for TO_INTEGER
        nibble := nibble + 2;
        -- if int_size or nibble_size were types it would require
        -- operator functions for those types.
        Report integer'IMAGE(TO_INTEGER(nibble));
        wait;
    end process;

end architecture fum;

添加了：

这是对BennyBarns在对该问题的评论中的断言的回应：“我想补充一点，虽然您可以在VHDL中使用n维数组，但只有第一个可能不受约束。”

与断言相反：

entity t1 is
end entity;

architecture foo of t1 is

    type typeI is array ( natural range <>, natural range <>) of integer;

begin
    process is
        variable sigI : typeI(0 to 1, 0 to 1);  -- 2D integer array
    begin
        sigI(0,0) := 1;
        sigI(0,1) := 2;
        sigI(1,0) := 3;
        sigI(1,1) := 4; 
        report "Initialized indiviually";
        report "sigI(0,0) = " & integer'IMAGE(sigI(0,0));
        report "sigI(0,1) = " & integer'IMAGE(sigI(0,1));
        report "sigI(1,0) = " & integer'IMAGE(sigI(1,0));
        report "sigI(1,1) = " & integer'IMAGE(sigI(1,1));
        sigI := ((11,12),(13,14));
        report "Initialized as an aggregate";
        report "sigI(0,0) = " & integer'IMAGE(sigI(0,0));
        report "sigI(0,1) = " & integer'IMAGE(sigI(0,1));
        report "sigI(1,0) = " & integer'IMAGE(sigI(1,0));
        report "sigI(1,1) = " & integer'IMAGE(sigI(1,1));
        wait;
    end process;
end architecture;

该语句不精确，并且在示例子类型声明中与包numeric_std中UNSIGNED的类型声明中的延迟范围约束相关。子类型指示需要由类型标记提供或明确提供的约束。它仅对作为无约束类型的子类型指示类型标记有效。

无约束类型的子类型声明必须提供约束，就像添加了

一样

signal A: unsigned;

作为实体foo的fum的架构声明项：

ghdl -a foo.vhdl
foo.vhdl:24:12: declaration of signal "a" with unconstrained array type "unsigned" is not allowed

只是为了让事情变得有趣，界面列表可能很特别：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fie is
    port (
        a:  in  unsigned
    );
end entity;

architecture fee of fie is

begin

EVAL:
    process (a)
    begin
        report "Fie:a range is " & integer'IMAGE(a'LEFT) & " to " & 
                                  integer'IMAGE(a'RIGHT) ;
    end process;

end architecture fee;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fie_tb is
end entity;

architecture fum of fie_tb is
    component fie is
        port (a: in unsigned);
    end component;

    signal aa:  unsigned (3 to 7);
begin

EUT: fie port map (a => aa);

end architecture;

“规则”可以在LRM部分的索引约束和离散范围，IEEE Std 1076-2008 5.3.2.2，-2002 / -1993 3.2.1.1中找到。

vhdl ::创建一个带有size参数的类型

1 个答案: