我正在为测试平台编写总线功能模型,我正在使用一个过程来处理读写操作,理想情况下我想使用一个声明为inout的总线。
我正在使用记录类型来实例化我的总线,但是当我在我的过程调用中将其声明为inout参数时,它似乎适用于来自过程的输出信号,但不识别过程中的输入。任何信号输入都是未初始化的" U"。我知道合成这个方法不起作用,但对于测试平台我认为可以将总线实例化为inout。
我的记录类型和过程实例化如下:
type t_apbp_intf is record
-- APB-pipe Interface
paddr : std_logic_vector(31 downto 0);
psel : std_logic;
penable : std_logic;
pwrite : std_logic;
pwdata : std_logic_vector(31 downto 0);
pstrb : std_logic_vector(3 downto 0);
prdata : std_logic_vector(31 downto 0);
pready : std_logic;
pslverr : std_logic;
prdvld : std_logic;
end record t_apbp_intf;
procedure nai_bus_cyc(
wr_rd_n : in std_logic;
addr_in : in std_logic_vector(31 downto 0); -- Address
data_in : in std_logic_vector(31 downto 0); -- Data to be written
signal tb_m_apbp : inout t_apbp_intf) is
begin
if wr_rd_n = C_BUS_WR then
wait until rising_edge(tb_clk);
tb_m_apbp.paddr <= addr_in;
tb_m_apbp.psel <= '1';
tb_m_apbp.penable <= '1';
tb_m_apbp.pwrite <= '1';
tb_m_apbp.pwdata <= data_in;
tb_m_apbp.pstrb <= "1111";
wait until rising_edge(tb_clk) and (tb_m_apbp.pready = '1');
tb_m_apbp.paddr <= (others => '0');
tb_m_apbp.psel <= '0';
tb_m_apbp.penable <= '0';
tb_m_apbp.pwrite <= '0';
tb_m_apbp.pwdata <= (others => '0');
tb_m_apbp.pstrb <= "0000";
else
wait until rising_edge(tb_clk);
tb_m_apbp.paddr <= addr_in;
tb_m_apbp.psel <= '1';
tb_m_apbp.penable <= '1';
tb_m_apbp.pwrite <= '0';
tb_m_apbp.pwdata <= (others => '0');
tb_m_apbp.pstrb <= "0000";
wait until rising_edge(tb_clk) and (tb_sprvalid_bus = '1');
tb_m_apbp.paddr <= (others => '0');
tb_m_apbp.psel <= '0';
tb_m_apbp.penable <= '0';
tb_m_apbp.pwrite <= '0';
tb_m_apbp.pwdata <= (others => '0');
tb_m_apbp.pstrb <= "0000";
end if;
end procedure;