使用时钟的边沿触发的动作时间

时间:2013-07-09 18:20:44

标签: verilog clock timing edge

假设我的代码如下:

always @(clock)
begin
  if (condition is met)
     a <= 0
  else if (another condition is met)
     b <= 0
end

我希望在时钟的posedge处有一个&lt; = 0,在时钟的边缘处b <= 0。我该如何指定?

我现在正在做的是......

always @(clock)
begin
   if (condition is met)
      @(posedge clock) a <= 0
   else if (another condition is met)
      @(negedge clock) b <= 0
end

1 个答案:

答案 0 :(得分:3)

使用两个always块。一个用于posedge,另一个用于negedge

always @(posedge clock) begin
  if (condition is met)
     a <= 0;
end
always @(negedge clock) begin
  if (!(condition is met) && (another condition is met))
     b <= 0;
end