在VHDL中检查记录数组的每个元素是否为0

时间:2013-06-24 17:45:30

标签: arrays record vhdl

在VHDL中,我有一个记录数组。我想做一个if语句,我在整个数组的每个索引处检查该记录的某些元素是'0'。我怎样才能做到这一点? 所以,如果我有

type offset_t is record
 a : std_logic;
 b : std_logic;
end record

type offset_array is (7 downto 0) of offset_t;

type blah is record
 offset2 : offset_array;
end record

如何检查offset2(7 downto 0)的“a”元素是否为0?什么是if语句? 我尝试使用'range和其他方式,但无法让它工作。

3 个答案:

答案 0 :(得分:3)

如果您只想检查a元素,则必须迭代:

for i in a.offset2'range loop
   assert a.offset2(i).a = '0';
end loop;

如果要检查所有地方的所有内容为零,请创建一个常量:

constant all_zeros : blah := (offset2 => (others => (others => '0')));

然后你可以与它比较:

assert a = offset2;

答案 1 :(得分:0)

试试a.offset2 = (7 downto 0 => (a => '0', b => '0'));。 您在数据类型示例中遇到了一些错误。下面的代码应该有效。

architecture RTL of demo is
    type offset_t is record
        a : std_logic;
        b : std_logic;
    end record;

    type offset_array is array (7 downto 0) of offset_t;
    type blah is record
        offset2 : offset_array;
    end record;
    signal a : blah;
begin
    a.offset2 <= (others => (a => '0', b => '0'));
    assert a.offset2 = (7 downto 0 => (a => '0', b => '0'));
end architecture RTL;

答案 2 :(得分:0)

这是一个建议你可以轻松插入if语句的函数(查找aElementOfOffset2IsZero)。

architecture rtl of if_record_array_record is

    type offset_t is record 
        a : std_logic; 
        b : std_logic; 
    end record;

    type offset_array is array(7 downto 0) of offset_t;
    type blah is record 
        offset2 : offset_array; 
    end record;

    function aElementOfOffset2IsZero(
        record_array_record : blah
    ) return boolean is
    variable result : boolean := TRUE;
    begin
        for i in 0 to record_array_record.offset2'length loop
            if record_array_record.offset2(i).a = '1'  then
                result := FALSE;
            end if;

        end loop;

        return result;

    end function;

    signal ablah : blah;

begin  

    process
    begin
        --if statement you wanted
        if aElementOfOffset2IsZero( ablah ) then
            --...
        end if;
        wait;
    end process;

end architecture rtl;