Question

假设gclk的完整0到15计数为输出pwm波的一个周期， pwmin反映了工作周期。随着计数从15 + 1减少到0首先 bufferreg值在gclk的上升沿获取pwmin值，并在每个连续的时钟边沿检查countreg值并根据该值给出pwmout

entity pwm is
port(gclk: in std_logic;
reset: in std_logic;
pwmin: in std_logic_vector(3 downto 0); --input reg to reflect the duty cycle
pwmout: out std_logic );
end pwm;

architecture Behavioral of pwm is
signal bufferreg,countreg: unsigned(3 downto 0);

signal count: integer:=16; -- count value for the one full cycle of PWM
begin
    process(gclk, reset, pwmin)
    begin
    case reset is --asynchronous reset 
    when '0' =>
            loop1: for count in 16 downto 0 loop --count is 15+1
                        if (rising_edge(gclk)) then --the buffer reg is loaded athe first clock edge
                                if (count=16) then
                                bufferreg<=unsigned(pwmin);
                                countreg<="0000";
                                else 
                                            if (countreg<=bufferreg) then
                                                        pwmout<='1'; --output high for on period
                                            elsif (countreg>bufferreg) then
                                                        pwmout<='0'; --output low for off period
                                            end if;
                                         countreg<=countreg+1 --updating of countreg
                                end if;
                         end if;
                     --next;
            end loop loop1;
    when others => 

    end case;   

end process;


end Behavioral;

Answer 1

你应该像下面这样编写你的代码：

process(gclk, reset)
begin
    if reset='1' then -- asynchronous reset, high active
       ...
    elsif rising_edge(gclk) then -- synchronous stuff on rising edge
        loop1: for count...
            ...

要知道你的“16次downto 0循环计数”导致17步！

我正在编写一个代码来生成VHDL中的PWM波，但是我的pwmout节点出现了错误的同步描述错误

1 个答案: