Question

我用Xilinx ISE 13.1合成了我的设计。目标设备是Virtex 5.然后我遇到了这个警告：

 WARNING:Xst:819 - "F:/FRONT-END/h264/inter/src/eei/eei_mvd.vhd" 
line 539: One or more signals are missing in the process sensitivity list. 
To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. 
Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:    
<mvd_l0<3><3>>, <mvd_l0<3><2>>, <mvd_l0<3><1>>, <mvd_l0<3><0>>, <mvd_l0<2><3>>, <mvd_l0<2><2>>,
 <mvd_l0<2><1>>, <mvd_l0<2><0>>, <mvd_l0<1><3>>, <mvd_l0<1><2>>, <mvd_l0<1><1>>, <mvd_l0<1><0>>,
 <mvd_l0<0><3>>, <mvd_l0<0><2>>, <mvd_l0<0><1>>, <mvd_l0<0><0>>, <mvd_l1<3><3>>, <mvd_l1<3><2>>,
 <mvd_l1<3><1>>, <mvd_l1<3><0>>, <mvd_l1<2><3>>, <mvd_l1<2><2>>, <mvd_l1<2><1>>, <mvd_l1<2><0>>,
 <mvd_l1<1><3>>, <mvd_l1<1><2>>, <mvd_l1<1><1>>, <mvd_l1<1><0>>, <mvd_l1<0><3>>, <mvd_l1<0><2>>, 
<mvd_l1<0><1>>, <mvd_l1<0><0>>, <mvd<0>>, <mvd<1>>

这是我的源代码：

proc_update_next: process(mvd_l0, mvd_l1, mvd, subMBPart_Idx, MBPart_Idx, eei_info )
  begin
    --// Init
    next_mvd_l0 <= mvd_l0;
    next_mvd_l1 <= mvd_l1;
    --// Change
    if eei_info.mb_type =  BLK_8x8 then
      for  i in 3 downto 0 loop
        for  j  in 3 downto 0  loop
          if i = to_integer(unsigned(MBPart_Idx))  and j = to_integer(unsigned(subMBPart_Idx)) then
            next_mvd_l0(i)(j)  <=  mvd(0);
            next_mvd_l1(i)(j)  <=  mvd(1);
          end  if;
        end  loop;
      end loop;
    else
      for  i in 3 downto 0 loop
        if i = to_integer(unsigned(MBPart_Idx)) then
          next_mvd_l0(i)(0)  <=  mvd(0);
          next_mvd_l1(i)(0)  <=  mvd(1);
        end  if;
      end loop;
    end if;
  end process;

更新：我在代码中更改了一点，但仍然是这个警告。

mvd_l0和mvd_l1是二维数组，它出现在敏感度列表中。我知道我的源代码太抽象了，ISE可能无法理解。

我尝试使用Virtex 7（在实验室中不可用），然后没有错误。所以，我的问题是如何修复此警告？我不能忽视这个警告，因为它可能导致锁定。

Answer 1

使用VHDL-2008构造process(all)告诉您希望灵敏度列表包含所有读取信号的工具。

或者，将其设为时钟进程，仅对时钟敏感，然后您也不必担心。

Answer 2

对于一组条件，您应该只为next_mvd_l0和next_mvd_l1设置一次信号。 “init”部分仍然是一个问题。如果您避免重置过程，最好使用局部变量。

最佳选择：在灵敏度列表中添加重置，如果已启用，请将next_mvd_ *设置为初始值

--// Init
if (reset = '1') then
    next_mvd_l0 <= mvd_l0;
    next_mvd_l1 <= mvd_l1;
end if;

第二个选项：使用局部变量

proc_update_next: process(mvd_l0, mvd_l1, mvd, subMBPart_Idx, MBPart_Idx, eei_info )
    variable mvd_10_local : 2dArrayType;
    variable mvd_11_local : 2dArrayType;
begin
    --// Init
    mvd_10_local := mvd_l0;
    mvd_11_local := mvd_l1;
    --// Change
    if eei_info.mb_type =  BLK_8x8 then
        for  i in 3 downto 0 loop
            for  j  in 3 downto 0  loop
                if i = to_integer(unsigned(MBPart_Idx))  and j = to_integer(unsigned(subMBPart_Idx)) then
                    mvd_10_local(i)(j)  :=  mvd(0);
                    mvd_11_local(i)(j)  :=  mvd(1);
                end  if;
            end  loop;
        end loop;
    else
        for  i in 3 downto 0 loop
            if i = to_integer(unsigned(MBPart_Idx)) then
                    mvd_10_local(i)(j)  :=  mvd(0);
                    mvd_11_local(i)(j)  :=  mvd(1);
            end  if;
        end loop;
    end if;
    next_mvd_l0 <= mvd_10_local;
    next_mvd_l1 <= mvd_l1_local;
end process;

Answer 3

您使用VHDL记录构造（eei_info.mb_type）。您可以将每个记录元素添加到sens-list以使xst满意。我只是忽略了这个警告。

如何解决Xilinx ISE关于灵敏度列表的警告？

3 个答案: