Question

我想尽快制作24条线，但我不断收到错误：

错误（10170）：在文本“=”附近的your_ALU_mux.v（81）处的Verilog HDL语法错误;期待“。”或标识符

这是我的代码：

module your_ALU_mux(your_out, operandA, operandB, opcode, switches, address);
input [7:0] operandA, operandB, address;
input [3:0] opcode, switches;
output [7:0] your_out;

wire [0:7] Bnot, newb, newa;
wire Cin, Cout;

    not
       (Bnot[0], operandB[0]),
       (Bnot[1], operandB[1]),
       (Bnot[2], operandB[2]),
       (Bnot[3], operandB[3]),
       (Bnot[4], operandB[4]),
       (Bnot[5], operandB[5]),
       (Bnot[6], operandB[6]),
       (Bnot[7], operandB[7]);

// Getting A' and B'
    if (address == 16'h00 || address == 16'h01)
    // Add A + B
    if (address == 16'h00)

        // newa = A
        newa[0] = operandA[0];
        newa[1] = operandA[1];
        newa[2] = operandA[2];
        newa[3] = operandA[3];
        newa[4] = operandA[4];
        newa[5] = operandA[5];
        newa[6] = operandA[6];
        newa[7] = operandA[7];

        // newb = B'
        newb[0] = Bnot[0];
        newb[1] = Bnot[1];
        newb[2] = Bnot[2];
        newb[3] = Bnot[3];
        newb[4] = Bnot[4];
        newb[5] = Bnot[5];
        newb[6] = Bnot[6];
        newb[7] = Bnot[7];

        // Carry in = 1
        Cin = 1;


        // A-B
    else if (address == 16'h01)
        // newb = B
        newb[0] = operandB[0];
        newb[1] = operandB[1];
        newb[2] = operandB[2];
        newb[3] = operandB[3];
        newb[4] = operandB[4];
        newb[5] = operandB[5];
        newb[6] = operandB[6];
        newb[7] = operandB[7];

        // newa = A
        newa[0] = operandA[0];
        newa[1] = operandA[1];
        newa[2] = operandA[2];
        newa[3] = operandA[3];
        newa[4] = operandA[4];
        newa[5] = operandA[5];
        newa[6] = operandA[6];
        newa[7] = operandA[7];

        // Carry in = 0
        Cin = 0;



end
        RippleCarryAdd A+B(.S0(your_out[0]), .S1(your_out[1],.S2(your_out[2],.S3(your_out[3],.S4(your_out[4],.S5(your_out[5]
                                    S6.(your_out[6]), S7.(your_out[7],
                                    .Cout(Cout),.Cin(Cin),
                                    .A0(newa[0]),.A1(newa[1]),.A2(newa[2]),.A3(newa[3]),.A4(newa[4]),.A5(newa[5]),
                                    .A6(newa[6]),.A7(newa[7]),
                                    .B0(newb[0]),.B1(newb[1]),.B2(newb[2]),.B3(newb[3]),.B4(newb[4]),
                                    .B5(newb[5]),.B6(newb[6]),.B7(newb[7]));

endmodule

我也错误地说：

错误（10170）：在文本“if”附近的your_ALU_mux.v（66）处的Verilog HDL语法错误;期待“endmodule”

它带给我的第一个if语句。

这是创建电线及使用它们的错误方法吗？

Answer 1

为了使您的代码更紧凑，您知道：

always @* begin 
  newa[0] = operandA[0];
  newa[1] = operandA[1];
  newa[2] = operandA[2];
  newa[3] = operandA[3];
  newa[4] = operandA[4];
  newa[5] = operandA[5];
  newa[6] = operandA[6];
  newa[7] = operandA[7];
end

与：

相同

reg newa[7:0]
always @* begin
  newa[7:0] = operandA[7:0];
end

作为电线：

wire newa[7:0]
assign newa[7:0] = operandA[7:0];

如果使用全宽，则位选择[7:0]是可选的。

Answer 2

if语句需要位于always块内，它们不能只是模块的一部分
在编写多行情况时，您需要在begin和end语句中包装语句（在其他编程语言中认为它们类似于{和}）
您似乎在RippleCarryAdd之前没有end的随机begin语句

如何在Verilog中快速制作多条线？

2 个答案: