Question

我正在尝试使用xilinix 10.1实现有限状态机标识符我在之前的问题中看到了这些错误，但答案中没有包含我的问题..我不是在寻找答案，而是为FFd1部分提供了意义

生成以下错误

WARNING:Xst:1293 - FF/Latch <machine1/current_state_FFd1> has a constant value of 0 in block <Main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <machine1/current_state_FFd2> has a constant value of 0 in block <Main>. This FF/Latch will be trimmed during the optimization process.

这是我的代码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity M_1 is
    Port ( x : in  STD_LOGIC;
       clk : in  STD_LOGIC;
       state : out  integer range 0 to 5 := 0;
       z : out  STD_LOGIC );
end M_1;

architecture Behavioral of M_1 is

 type state_type is (A, B, C, D);
 signal next_state, current_state: state_type := A;

begin

process(clk) is
begin
if (clk = '1' and clk'event) then
    current_state <= next_state;
end if;
end process;

process(x,current_state)
begin
case current_state is
    when A =>
        if(x='0') then
            next_state <= B;
            z <='0';
        elsif(x='1') then
            next_state <= C;
            z <='1';            
        end if;
    when B =>
        if(x='0') then
            next_state <= C;
            z <='1';
        elsif(x='1') then
            next_state <= D;
            z <='0';            
        end if;
    when C =>
        if(x='0') then
            next_state <= A;
            z <='0';
        elsif(x='1') then
            next_state <= D;
            z <='1';            
        end if;
    when D =>
        if(x='0') then
            next_state <= B;
            z <='0';
        elsif(x='1') then
            next_state <= C;
            z <='0';            
        end if;
    end case;
end process;

process (current_State) is
begin
    case current_state is
    when A =>
        state <=0;
    when B =>
        state <=1;
    when C =>
        state <=2;
    when D =>
        state <=3;
    end case;
end process;

end Behavioral;

任何人都可以告诉我

current_state_FFd1和它与current_State_1之间有什么区别？
我该如何解决这个错误？

非常感谢

Answer 1

“current_state”信号由CAD工具映射到2位触发器基元上。触发器看起来像the FD16CE primitive, shown here。

触发器将采用2个数据输入（current_state_FFd1和current_state_FFd2）和一个时钟，并产生两个数据输出（current_state_FFq1和current_state_FFq2）。输入决定在下一个时钟边沿采样的current_state信号的值，输出反映当前状态。

您看到的消息表明CAD工具可以证明“current_state”永远不会改变“00”编码（枚举类型中的“A”），因此触发器可以通过硬连线输出“00”。

您发布的VHDL看起来很合理 - “x”输入的更改应该会导致current_state发生变化。我敢打赌，'x'输入在某种程度上硬连接到更高级VHDL（或在你的测试平台中）。

FFd1在VHDL中的含义警告FF / Latch的常数值为0

1 个答案: