如何从HDL（Verilog或VHDL）转换为FIRRTL（.fir）？

Question

我目前正在研究一个有关RTL优化的项目，并且正在使用一个工具，该工具将电路的FIRRTL表示作为输入。

我正在寻找一种给出给定Verilog / VHDL描述并将其转换为.fir的工具

我已经找到的是Verilator，它从Verilog转换为CPP。 从Scala转换为Verilog的凿子，但不是我所需要的

鉴于FIRRTL是中间表示，我不知道是否有办法像VIVADO或Modelsim这样从CAD中提取它

编辑：尝试使用YOSYS生成的.fir文件时出现错误日志：

'maku@Maku:~/Desktop/Fuzzing/rfuzz$ make run 

cd instrumentation ;\

sbt -ivy /home/maku/Desktop/Fuzzing/rfuzz/.ivy2 "runMain hardwareafl.firrtltransforms.CustomTop -i /home/maku/Desktop/Fuzzing/rfuzz/benchmarks/Top_PipelinedCipher.fir -o /home/maku/Desktop/Fuzzing/rfuzz/build/Top_PipelinedCipher.v -X verilog -ll info -fct hardwareafl.firrtltransforms.NoDedupTransform,hardwareafl.firrtltransforms.ReplaceMemsTransform,hardwareafl.firrtltransforms.SplitMuxConditions,hardwareafl.firrtltransforms.ProfilingTransform,firrtl.passes.wiring.WiringTransform,hardwareafl.firrtltransforms.AddMetaResetTransform "

[info] Loading settings from plugins.sbt ...

[info] Loading project definition from /home/maku/Desktop/Fuzzing/rfuzz/instrumentation/project

[info] Loading settings from build.sbt ...

[info] Set current project to instrumentation (in build file:/home/maku/Desktop/Fuzzing/rfuzz/instrumentation/)

[info] Running hardwareafl.firrtltransforms.CustomTop -i /home/maku/Desktop/Fuzzing/rfuzz/benchmarks/Top_PipelinedCipher.fir -o /home/maku/Desktop/Fuzzing/rfuzz/build/Top_PipelinedCipher.v -X verilog -ll info -fct hardwareafl.firrtltransforms.NoDedupTransform,hardwareafl.firrtltransforms.ReplaceMemsTransform,hardwareafl.firrtltransforms.SplitMuxConditions,hardwareafl.firrtltransforms.ProfilingTransform,firrtl.passes.wiring.WiringTransform,hardwareafl.firrtltransforms.AddMetaResetTransform

[error] (run-main-0) java.lang.StackOverflowError

[error] java.lang.StackOverflowError

[error]     at java.util.regex.Pattern$5.isSatisfiedBy(Pattern.java:5253)

[error]     at java.util.regex.Pattern$5.isSatisfiedBy(Pattern.java:5253)

[error]     at java.util.regex.Pattern$CharProperty.match(Pattern.java:3778)

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