Question

我正在尝试运行此代码并且它会给出以下错误：＆＃34; always＆＃34;附近的语法错误＆＃34; endmodule＆＃34;

附近的语法错误

我不明白这段代码有什么问题。这是代码：

module fortran_v2(
    input clk
    );
parameter N=8;
parameter M=6;
parameter size=1000;     
reg [N-1:0] A [0:size-1];
reg [N-1:0] B [0:size-1];
reg [M-1:0] C [0:size-1];
reg [M-1:0] D [0:size-1];
reg [15:0] k=0;
integer open_file;
initial begin
open_file= $fopen("output.txt","w");
end

always @ (posedge clk) begin
if(k<1000)
k<=k+1;
else
k<=1000;
end

always @ (posedge clk) begin
if(k<1000) begin
  A[k]<=$random;
  B[k]<=$random;
  end

always @ (posedge clk) begin
if (k<1000) begin
  C[k]<=A[k]*B[k] +5;
  D[k]<=A[k]+B[k] -5;
  $fwrite(open_file,"A[%d",k,"]",A[k],"B[%d",k,"]",B[k],"C[%d",k,"]",C[k],"D[%d",k,"]",D[k]);
end
else
  A[k]=0;
end  
endmodule

Answer 1

如果使用适当的缩进，您就没有问题。在您的always个区块中，缺少关键字end：

always @ (posedge clk) begin
  if(k<1000) begin
    A[k]<=$random;
    B[k]<=$random;
  end
end //missing end

Answer 2

开始......在Verilog中结束对应于大多数编程语言{...}中的花括号，因此每个“begin”必须有一个与它相关联的“end”。

Answer 3

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    13:54:23 03/14/2017 
// Design Name: 
// Module Name:    hhi 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

         module pulse(input wire [1:0] sel,         // No need for the sel to be wire 
        input   clk,
        input rst_n,
        output reg [13:0] Q,    
        output reg pulse,   
        input   input_stb,                  // Input is valid
        input   output_ack,     
        output  output_stb,         
        output  input_ack);                // 2 Flag model 

reg s_input_ack ;
reg s_output_stb;
 parameter get_inputs         = 4'd0,
        counter               = 4'd1;

always @(posedge clk , negedge rst_n)
begin

case (state)
    get_inputs:
    s_input_ack <= 1;
    if (s_input_ack && input_a_stb) 
    begin
    s_input_ack <= 0;
            case(sel)
            00: Q <= 14'd11;//00000000001010;
            01: Q <= 14'd101;//00000001100100;
            10: Q <= 14'd1001;//00001111101000;
            11: Q <= 14'd10001;//10011100010000;
            default: Q <= 14'd0;    
            endcase
    state <= counter;
    end

    counter:
        begin
        s_output_stb <= 1;
        if (s_output_stb && output_z_ack)
            begin
                        s_output_stb <= 0;

                if(Q != 14'h1 && Q != 14'h0)
                    begin
                    Q <= Q - 1'b1;
                    pulse  <= 1'b1;
                    end
                else
                    begin
                    pulse <= 1'b0;
                    end
                end
        state <= get_inputs;
        end 

endcase
        if(!rst_n)
    begin
        Q <= 14'h0;
        pulse <= 1'b0;
              s_input_ack <= 0;
              s_output_stb <= 0;
    end
      assign input_ack = s_input_ack;







error  in <= synbol

Verilog代码中的语法错误

3 个答案: