如何初始化std_logic_vector？

Question

我有这段代码

--RAM module
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;

entity RAM is
  generic(
    address_length, data_length : integer);
  port(
    addr       : in    std_logic_vector(address_length-1 downto 0);
    dat        : inout std_logic_vector(data_length-1 downto 0);
    rd, wr, en : in    bit);
end entity RAM;

architecture RAM_impl of RAM is
  type mem is array(2**address_length-1 downto 0) of std_logic_vector(data_length-1 downto 0);
begin
  process(rd, wr, en)is
    variable cont : mem;
  begin
    if(en = '1')then
      if(wr = '1' and rd = '0')then
        cont(to_integer(unsigned(addr))) := dat;
      end if;
      if(rd = '1' and wr = '0')then
        dat <= cont(to_integer(unsigned(addr)));
      end if;
    end if;
  end process;
end architecture RAM_impl;


--Test module
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;

entity Example4RAM is
end entity Example4RAM;

architecture Tester of Example4RAM is
  signal rd, wr, en : bit;
  signal str        : std_logic_vector(15 downto 0);
  signal ext        : std_logic_vector(7 downto 0);
begin
  module : entity work.RAM(RAM_impl)
    generic map(
      address_length => 16,
      data_length    => 8)
    port map(str, ext, rd, wr, en);
  tt : process is
  begin
    str <= X"0001";
    ext <= "00000000";
    rd  <= '0'; wr <= '1';
    wait for 5 ns;
    en  <= '1';
    wait for 5 ns;
    rd  <= '0'; wr <= '0';
    wait for 10 ns;
    rd  <= '1'; wr <= '0';
  end process;
end architecture Tester;

当我在这个RAM模块上运行模拟时，str矢量初始化很好但是ext矢量保持未初始化。在RAM模块中，str在向量中，而ext是在向量中。这是以某种方式制造问题，是否有人知道解决方案？ （自昨天以来我确实改变了来源，但它仍无效）

Answer 1

我添加了一个RAM模块并稍微修改了测试激励（当wr无效时，ext被驱动到所有'Z'（行为模型不需要保持）。

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity RAM is
    generic (
        constant address_length:    natural := 16;
        constant data_length:       natural := 8
    );
    port (
        signal str:     in      std_logic_vector (address_length-1 downto 0);
        signal ext:     inout   std_logic_vector (data_length-1  downto 0);
        signal rd:      in      BIT;
        signal wr:      in      BIT
    );
end entity; 

architecture RAM_impl of RAM is
    type ram_array is array (natural range address_length-1 downto 0) 
        of std_logic_vector (data_length-1 downto 0);
    signal mem_array: ram_array;
begin


MEMORY:
    process (str, ext, rd, wr)
        variable addr:  natural range 0 to 2**address_length -1 ;
    begin
        addr := TO_INTEGER(UNSIGNED(str));  -- heed the warnings
        if wr = '1' then
            mem_array(addr) <= ext;
        end if;
        if rd = '0' then
            ext <= (others => 'Z');
        else
            ext <= mem_array(addr);
        end if;
    end process;


end architecture;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use IEEE.numeric_std.ALL;

entity Example4RAM is
end entity Example4RAM;

architecture Tester of Example4RAM is
signal rd,wr,clk: bit;
signal str: std_logic_vector(15 downto 0);
signal ext: std_logic_vector(7 downto 0);
begin

module: 
    entity work.RAM(RAM_impl) 
        generic map (
            address_length=>16,
            data_length=>8
        )
        port map (
            str,
            ext,
            rd,
            wr
        )
    ;

tt:
    process
    begin
        str<=X"0001";
        ext<="00000000";
        wait for 5 ns;
        rd<='0';wr<='1';
        wait for 5 ns;
        rd<='0';wr<='0';
        ext <= (others => 'Z');  -- ADDED
        wait for 10 ns;
        rd<='1';wr<='0'; 
        wait for 20 ns;  -- ADDED
        str <=X"0002";   -- ADDED
        wait for 20 ns;  -- ADDED
        wait;
    end process;
end architecture Tester;

对刺激的改变包括改变RAM地址，表明读取未初始化的位置会返回'U'（波形上的uu）：

ghdl -a exampleram.vhdl
ghdl -r Example4RAM --wave=Example4RAM.ghw
../../../../libraries/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning):   
NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
open *.ghw

基本上，当任何一个人不应该驱动一个值时，进程和RAM驱动器都会使用所有'Z'。在读取之前写入会隐藏str地址X“0001”中的“U”值。如您所见，如果地址更改为未初始化的位置，则会显示“U”。分辨率提供RAM读取数据或将写入数据提供给双向数据总线（ext）上的RAM阵列。

（这是在带有ghdl mcode版本的Mac上完成的（直接编译，就像Windows一样，不需要明确的详细说明），并使用GTKWave显示。）

断言警告（检测到元值）来自在零时间（@ 0ms）分配给str（所有'U'）的默认值。