D触发器在模拟时不起作用，modelsim

Question

我一直试图让它起作用，但是当我模拟我的代码时，两个触发器之一不起作用。如屏幕截图所示，当输入为 0 时，输出为 1，这不是它应该的工作方式。

entity practica2 is
port (clk, rst: in std_logic;
      x: in std_logic_vector (1 downto 0);
      z: out std_logic);
end practica2;

architecture apartadoB of practica2 is
signal s: std_logic_vector (3 downto 0);
signal q: std_logic_vector (1 downto 0);
signal nq: std_logic_vector (1 downto 0);
signal nx: std_logic_vector (1 downto 0);
signal qp: std_logic_vector (1 downto 0);
begin  

     not_x1: entity work.not1 port map(x(1), nx(1));
     not_x0: entity work.not1 port map(x(0), nx(0));
     not_q1: entity work.not1 port map(q(1), nq(1)); 
     not_q0: entity work.not1 port map(q(0), nq(0));  
     
     and_1_q0: entity work.and3 port map(nq(0), nx(1), nx(0), s(1)); 
     and_2_q0: entity work.and3 port map(q(1), nx(1), nx(0), s(0));
     or_q0: entity work.or2 port map(s(1), s(0), qp(0));
     flip_d_q0: entity work.flipflopD port map(clk, rst, qp(0), q(0));

     and_1_q1: entity work.and4 port map(nq(1), q(0), nx(1), nx(0), s(3)); 
     and_2_q1: entity work.and4 port map(q(1), nq(0), nx(1), nx(0), s(2));
     or_q1: entity work.or2 port map(s(3), s(2), qp(1));
     flip_d_q1: entity work.flipflopD port map(clk, rst, qp(1), q(1)); 

     and_q1_q0: entity work.and2 port map(q(1), q(0), z);
end apartadoB;

这是我的练习代码。这是触发器代码，我无法更改：

entity flipflopD is
port(clk, rst, D: in  std_logic;
     Q:           out std_logic);
end flipflopD;

architecture funcional of flipflopD is
begin
process(clk,rst)
    begin
        if rst = '1' then
            Q <= '0';
        elsif rising_edge(clk) then
            Q <= D;
        end if;
    end process;
end funcional;

这是模拟，在flip_d_q1中，D是'0'，Q是'1'：