我的测试台只显示不关心我的输入

时间:2021-05-15 14:35:02

标签: verilog questasim

当我测试我的数据流模块时,我的所有输入都是无关紧要的。我不确定问题出在哪里。是我的方程式还是我的测试平台本身?

这是我的代码。

数据流:

module TollSystem(weekDay,rushHour,lateNight,highTraffic,lowRate,mediumRate,highRate);

input weekDay,rushHour,lateNight,highTraffic;

output lowRate,mediumRate,highRate;

assign #6 lowRate = ~weekDay&~rushHour&lateNight&~highTraffic | 
weekDay&~rushHour&lateNight&~highTraffic;

assign #6 mediumRate = (~rushHour&~lateNight&~highTraffic) | (~weekDay&~lateNight&~highTraffic) | 
(rushHour&lateNight);

assign #6 highRate = (weekDay&~lateNight&rushHour) | 
(~lateNight&highTraffic|~rushHour&lateNight&highTraffic);

endmodule

测试平台:

module TollSystemtest();

reg weekDay,rushHour,lateNight,highTraffic;

wire lowRate,mediumRate,highRate;

TollSystem TSys(weekDay,rushHour,lateNight,highTraffic,lowRate,mediumRate,highRate);

initial
begin

 weekDay=0;rushHour=0;lateNight=0;highTraffic=0;
 weekDay=0;rushHour=0;lateNight=0;highTraffic=1;
 weekDay=0;rushHour=0;lateNight=1;highTraffic=0;
 weekDay=0;rushHour=0;lateNight=1;highTraffic=1;
 weekDay=0;rushHour=1;lateNight=0;highTraffic=0;
 weekDay=0;rushHour=1;lateNight=0;highTraffic=1;
 weekDay=0;rushHour=1;lateNight=1;highTraffic=0;
 weekDay=0;rushHour=1;lateNight=1;highTraffic=1;
 weekDay=1;rushHour=0;lateNight=0;highTraffic=0;
 weekDay=1;rushHour=0;lateNight=0;highTraffic=1;
 weekDay=1;rushHour=0;lateNight=1;highTraffic=0;
 weekDay=1;rushHour=0;lateNight=1;highTraffic=1;
 weekDay=1;rushHour=1;lateNight=0;highTraffic=0;
 weekDay=1;rushHour=1;lateNight=0;highTraffic=1;
 weekDay=1;rushHour=1;lateNight=1;highTraffic=0;
 weekDay=1;rushHour=1;lateNight=1;highTraffic=1;



$finish();
end
endmodule

输入/输出结果:

[testBench output1

1 个答案:

答案 0 :(得分:0)

当我运行您的代码时,模拟在时间 0 结束。由于没有时间流逝,因此您的输入报告为 x/z 也就不足为奇了。您需要在测试平台中添加延迟。例如:

initial
begin
         weekDay=0;rushHour=0;lateNight=0;highTraffic=0;
    #20; weekDay=0;rushHour=0;lateNight=0;highTraffic=1;
    #20; weekDay=0;rushHour=0;lateNight=1;highTraffic=0;
    #20; weekDay=0;rushHour=0;lateNight=1;highTraffic=1;
    #20; weekDay=0;rushHour=1;lateNight=0;highTraffic=0;
    #20; weekDay=0;rushHour=1;lateNight=0;highTraffic=1;
    #20; weekDay=0;rushHour=1;lateNight=1;highTraffic=0;
    #20; weekDay=0;rushHour=1;lateNight=1;highTraffic=1;
    #20; weekDay=1;rushHour=0;lateNight=0;highTraffic=0;
    #20; weekDay=1;rushHour=0;lateNight=0;highTraffic=1;
    #20; weekDay=1;rushHour=0;lateNight=1;highTraffic=0;
    #20; weekDay=1;rushHour=0;lateNight=1;highTraffic=1;
    #20; weekDay=1;rushHour=1;lateNight=0;highTraffic=0;
    #20; weekDay=1;rushHour=1;lateNight=0;highTraffic=1;
    #20; weekDay=1;rushHour=1;lateNight=1;highTraffic=0;
    #20; weekDay=1;rushHour=1;lateNight=1;highTraffic=1;
    $finish();
end

现在,当我运行模拟并查看波形时,我看到所有信号都变为已知值。

我添加了 #20 的延迟,但您应该将其更改为对您的设计更有意义的内容。