Question

我是使用 VHDL 进行 FPGA 设计的新手，并且遇到了测试台仿真的问题：每次我尝试仿真我的模型（测试台编写者提供的测试台）时，我都会收到以下错误消息疯了：

错误：(vsim-3173) 实体 >'C:/intelFPGA_lite/progetto_dsp/simulation/modelsim/rtl_work.progetto_dsp_top_vhd_t>st' 没有架构。

我的模型是一个简单的相位频率检测器 (PFD)，我只想模拟它在不同输入信号下的行为。

在我发布我的测试平台代码之后，我从自动生成的代码中唯一改变的是添加了 A 和 B 信号（我将它们制作成具有不同频率的时钟信号）。

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

ENTITY progetto_dsp_top_vhd_tst IS
END progetto_dsp_top_vhd_tst;
ARCHITECTURE progetto_dsp_top_arch OF progetto_dsp_top_vhd_tst IS
-- constants    
constant period_A : time := 10 ps;
constant period_B : time := 20 ps;                                             
-- signals                                                   
SIGNAL A : STD_LOGIC;
SIGNAL B : STD_LOGIC;
SIGNAL High : STD_LOGIC;
SIGNAL QA : STD_LOGIC;
SIGNAL QB : STD_LOGIC;
COMPONENT progetto_dsp_top
    PORT (
    A : IN STD_LOGIC;
    B : IN STD_LOGIC;
    High : IN STD_LOGIC;
    QA : BUFFER STD_LOGIC;
    QB : BUFFER STD_LOGIC
    );
END COMPONENT;

--signal A generation
process
    begin
        A <= '1';
        wait for period_A/2;
        A <= '0';
        wait for period_A/2;
    end process;
     
--signal B generation
process
    begin
        B <= '1';
        wait for period_B/2;
        B <= '0';
        wait for period_B/2;
    end process;

BEGIN
    i1 : progetto_dsp_top
    PORT MAP (
-- list connections between master ports and signals
    A => A,
    B => B,
    High => High,
    QA => QA,
    QB => QB
    );
init : PROCESS                                               
-- variable declarations                                     
BEGIN                                                        
        -- code that executes only once                      
WAIT;                                                       
END PROCESS init;                                           
always : PROCESS                                              
-- optional sensitivity list                                  
-- (        )                                                 
-- variable declarations                                      
BEGIN                                                         
        -- code executes for every event on sensitivity list  
WAIT;                                                        
END PROCESS always;                                          
END progetto_dsp_top_arch;

实体在 Modelsim 仿真中没有架构

0 个答案: