尝试在modelsim中模拟我的测试平台时遇到问题，我收到错误消息，我的实体没有架构。测试平台在modelsim中完美编译，但当我开始模拟时，我得到了上面提到的错误。
如果你能帮助我，我将不胜感激。
实体在quartus ii中编译，测试台在modelsim中编译，但是当我在modelsim中模拟时，即使我选择了架构行为，它也说我无法模拟，因为它没有架构
library IEEE;
use IEEE.Std_logic_1164.all;
entity finalPipelines_tb is
end;
architecture bench of finalPipelines_tb is
component finalPipelines
Port(CLK, RST : in std_logic;
a,b,c,d,e,f,g,h,i : in std_logic_vector(7 downto 0);
suma : out std_logic_vector(7 downto 0);
cout : out std_logic);
end component;
signal CLK, RST: std_logic;
signal a,b,c,d,e,f,g,h,i: std_logic_vector(7 downto 0);
signal suma: std_logic_vector(7 downto 0);
signal cout: std_logic;
constant clock_period: time := 10 ns;
signal stop_the_clock: boolean;
begin
uut: finalPipelines port map ( CLK => CLK,
RST => RST,
a => a,
b => b,
c => c,
d => d,
e => e,
f => f,
g => g,
h => h,
i => i,
suma => suma,
cout => cout );
workflow: process
begin
RST <= '1';
a <= "00001000";
b <= "11111111";
wait for 20 ns;
c <= "00010101";
b <= "00010110";
wait for 20 ns;
a <= "00000000";
c <= "10001000";
stop_the_clock <= true;
wait;
end process;
clocking: process
begin
while not stop_the_clock loop
CLK <= '0', '1' after clock_period / 2;
wait for clock_period;
end loop;
wait;
end process;
end;
library IEEE;
use ieee.std_logic_1164.all;
entity finalPipelines is
Port(CLK, RST : in std_logic;
a,b,c,d,e,f,g,h,i : in std_logic_vector(7 downto 0);
suma : out std_logic_vector(7 downto 0);
cout : out std_logic);
end finalPipelines;
architecture rtl of finalPipelines is
signal FF1, FF2, FF3, FF4, FF5, FF6, FF7, FF8, FF9 : std_logic_vector(7 downto 0);
signal FF10, FF12, FF14, FF16, FF18, FF20 : std_logic_vector(11 downto 0);
signal FF11, FF13, FF15, FF17, FF19, FF21 : std_logic_vector(12 downto 0);
signal FFS : std_logic_vector (11 downto 0);
signal FFCo : std_logic_vector (12 downto 0);
signal s0, s1, s2, s3, s4, s5 : std_logic_vector(11 downto 0);
signal c0,c1,c2,c3,c4,c5 : std_logic_vector(12 downto 0);
signal s6 : std_logic_vector(11 downto 0);
signal c6 : std_logic_vector(12 downto 0);
component csa12bits
port(
A,B,C : in std_logic_vector(11 downto 0);
Suma : out std_logic_vector(11 downto 0);
Cout : out std_logic_vector(12 downto 0)
);
end component;
component rca
port(
a,b : in std_logic_vector(7 downto 0);
cin : in std_logic;
s : out std_logic_vector(7 downto 0);
cout: out std_logic);
end component;
begin
process(CLK,RST) begin
if RST = '0' then
FF1 <= x"00";
FF2 <= x"00";
FF3 <= x"00";
FF4 <= x"00";
FF5 <= x"00";
FF6 <= x"00";
FF7 <= x"00";
FF8 <= x"00";
FF9 <= x"00";
FF10 <= x"000" ;
FF11 <= x"000"&'0';
FF12 <= x"000" ;
FF13 <= x"000"&'0';
FF14 <= x"000" ;
FF15 <= x"000"&'0';
FF16 <= x"000" ;
FF17 <= x"000"&'0';
FF18 <= x"000" ;
FF19 <= x"000"&'0';
FF20 <= x"000" ;
FF21 <= x"000"&'0';
FFS <= x"000";
FFCo <= x"000"&'0';
elsif CLK'event and CLK = '1' then
FF1 <= a;
FF2 <= b;
FF3 <= c;
FF4 <= d;
FF5 <= e;
FF6 <= f;
FF7 <= g;
FF8 <= h;
FF9 <= i;
FF10 <= s0;
FF11 <= c0;
FF12 <= s1;
FF13 <= c1;
FF14 <= s2;
FF15 <= c2;
FF16 <= s3;
FF17 <= c3;
FF18 <= s4;
FF19 <= c4;
FF20 <= s5;
FF21 <= c5;
FFS <= s6;
FFCo <= c6;
end if;
end process;
I0: csa12bits port map (x"0"&FF1, x"0"&FF2, x"0"&FF3, s0, c0);
I1: csa12bits port map (x"0"&FF4, x"0"&FF5, x"0"&FF6, s1, c1);
I2: csa12bits port map (x"0"&FF7, x"0"&FF8, x"0"&FF9, s2, c2);
I3: csa12bits port map (FF10, FF11(11 downto 0), FF12, s3, c3);
I4: csa12bits port map (FF13(11 downto 0), FF14, FF15(11 downto 0), s4, c4);
I5: csa12bits port map (FF16, FF17(11 downto 0), FF18, s5, c5);
I6: csa12bits port map (FF20, FF19(11 downto 0), FF21(11 downto 0), s6, c6);
A0: rca port map (FFS(7 downto 0), FFCo(8 downto 1), FFCo(0), suma, cout);
end rtl;