在VHDL测试平台中，我具有一个解析csv文件以便初始化测试数组的函数。
在精化阶段运行该函数以设置常量值时，该函数的行为与在仿真中使用相同函数（例如在重置期间初始化信号）时的行为有所不同
功能代码为：
constant cn_DATA_WIDTH : natural := 10;
constant cn_DATA_DEPTH : natural := 400;
type tav_data_array is array (0 to cn_DATA_DEPTH - 1) of std_logic_vector(cn_DATA_WIDTH - 1 downto 0);
function f_init_data_from_file (
s_file_path : in string;
i_column_index : in integer := 0
) return tav_data_array is
-- file parsing
file f_data_file_buf : text is in s_file_path;
variable vl_data_file_line : line;
variable vi_data_entry : integer;
variable vc_comma : character;
variable vb_good_num : boolean;
-- destination
variable vav_data_array : tav_data_array;
begin
-- Skip first line that contains header
readline (f_data_file_buf, vl_data_file_line);
for line_index in vav_data_array'range loop
readline (f_data_file_buf, vl_data_file_line);
read (vl_data_file_line, vi_data_entry, vb_good_num);
assert vb_good_num
report "Failed reading file : " & s_file_path
& ", at line = " & integer'image(line_index)
& ", at column = 0"
severity failure;
for column_index in 1 to i_column_index loop
read(vl_data_file_line, vc_comma);
read(vl_data_file_line, vi_data_entry, vb_good_num);
assert vb_good_num
report "Failed reading file : " & s_file_path
& ", at line = " & integer'image(line_index)
& ", at column = " & integer'image(column_index)
severity failure;
end loop;
vav_data_array(line_index) := std_logic_vector(to_unsigned(vi_data_entry, cn_DATA_WIDTH));
end loop;
return vav_data_array;
end function;
详细说明功能用法：
constant cav_data : tav_data_array :=
f_init_data_from_file (
s_file_path => "my_path" ,
i_column_index => 3
);
结果：未使用预期的数据初始化测试数组。用于初始化的数据是第0列而不是第3列。
功能的详细说明：
signal sav_data : tav_data_array;
-- ...
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
sav_data <=
f_init_data_from_file (
s_file_path => "my_path" ,
i_column_index => 3
);
else
-- ...
end if;
end if;
end process;
在这种情况下，用于初始化的数据是正确的数据。按预期使用了第3列。
是否存在这种不同行为的原因？还是我用于仿真的工具（Xilinx Vivado 2018.2）中的错误？
编辑以创建MRVE：
根据要求，这是一个最小的可复制示例。一些参数
源代码：
-- MRVE
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- File parsing
use STD.textio.all;
use ieee.std_logic_textio.all;
entity file_bug_mrve is
end file_bug_mrve;
architecture a_file_bug_mrve of file_bug_mrve is
-- Actual data are 12 bits
constant cn_DATA_WIDTH : natural := 12;
constant cn_DATA_DEPTH : natural := 4; -- testbench is planned for 400 high priority cycles
type tav_data_array is array (0 to cn_DATA_DEPTH - 1) of std_logic_vector(cn_DATA_WIDTH - 1 downto 0);
-- Parse csv data file to retrieve all entries at specified columns
function f_init_data_from_file (
s_file_path : in string;
i_column_index : in integer := 0
) return tav_data_array is
-- file parsing
file f_data_file_buf : text is in s_file_path;
variable vl_data_file_line : line;
variable vi_data_entry : integer;
variable vc_comma : character;
variable vb_good_num : boolean;
-- destination
variable vav_data_array : tav_data_array;
begin
-- Skip first line
readline (f_data_file_buf, vl_data_file_line);
for line_index in vav_data_array'range loop
readline (f_data_file_buf, vl_data_file_line);
read (vl_data_file_line, vi_data_entry, vb_good_num);
assert vb_good_num
report "Failed reading file : " & s_file_path
& ", at line = " & integer'image(line_index)
& ", at column = 0"
severity failure;
for column_index in 1 to i_column_index loop
read(vl_data_file_line, vc_comma);
read(vl_data_file_line, vi_data_entry, vb_good_num);
assert vb_good_num
report "Failed reading file : " & s_file_path
& ", at line = " & integer'image(line_index)
& ", at column = " & integer'image(column_index)
severity failure;
end loop;
vav_data_array(line_index) := std_logic_vector(to_unsigned(vi_data_entry, cn_DATA_WIDTH));
end loop;
return vav_data_array;
end function;
constant cs_RSP_DATA_IN_FILE_PATH : string := "../../src/xls/file_bug_mrve.csv";
constant cn_RSP_DATA_IN_COLUMN_INDEX : natural := 3;
-- registers emulation
-- Setting init data to be processed in elaboration does not work
-- Data will be initialized with first column instead of third
signal sav_data : tav_data_array :=
f_init_data_from_file (
s_file_path => cs_RSP_DATA_IN_FILE_PATH ,
i_column_index => cn_RSP_DATA_IN_COLUMN_INDEX
);
-- infa Simulation
constant ct_CLOCK_PERIOD_100 : time := 10 ns;
constant ct_TEST_COMPLETION_TIME : time := ct_CLOCK_PERIOD_100 * 10;
signal s_clk : std_logic;
signal s_rst : std_logic;
signal sb_end : boolean := false;
begin
-- -----------------------------------------------------------------------------------------------------------------
-- Clock process definitions
-- -----------------------------------------------------------------------------------------------------------------
p_Clock_100 : process
begin
s_clk <= '0';
wait for ct_CLOCK_PERIOD_100/2;
s_clk <= '1';
wait for ct_CLOCK_PERIOD_100/2;
if sb_end then
wait;
end if;
end process;
-- -----------------------------------------------------------------------------------------------------------------
-- Main Stimulus process
-- -----------------------------------------------------------------------------------------------------------------
p_stimulous : process
begin
--
s_rst <= '0';
-- 1 clock cycle reset to avoid loading file multiple times
wait until rising_edge(s_clk);
s_rst <= '1';
wait until rising_edge(s_clk);
s_rst <= '0';
wait for ct_TEST_COMPLETION_TIME;
sb_end <= true;
end process;
p_main : process(s_clk)
begin
if rising_edge(s_clk) then
if s_rst = '1' then
-- Setting init data to be processed in simulation works
-- Data will be initialized with forth column as expected
sav_data <=
f_init_data_from_file (
s_file_path => cs_RSP_DATA_IN_FILE_PATH ,
i_column_index => cn_RSP_DATA_IN_COLUMN_INDEX
);
else
-- Nothing to do in MRVE
end if;
end if;
end process p_main;
end a_file_bug_mrve;
CSV文件：
Ch0,Ch1,Ch2,Ch3
1,5,9,13
2,6,10,14
3,7,11,15
4,8,12,16