Question

我使用的是英特尔Westmere处理器。 westmere的架构由2个芯片上的12个CPU核心组成。因此，这意味着每个芯片包含6个内核。

我不知道CPU内核是如何排序或编号的。我的猜测是它可以是以下任何一种：

核心0,1,2,3,4和5在一个芯片上，核心6,7,8,9,10和11在   在第二个芯片上

核心0,2,4,6,8和10在一个芯片上，核心1,3,5,7,9和11   是在第二个芯片上

有谁知道CPU内核的排序/编号

Answer 1

有关详细信息，您可以尝试使用此工具： http://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration

这是确定这一点的官方工具。

以下是运行CentOS 5.3的两台物理Intel X5560（6核+ 6HT）的机器运行示例（可能有点旧）。

Package 0 Cache and Thread details

Box Description:
Cache  is cache level designator
Size   is cache size
OScpu# is cpu # as seen by OS
Core   is core#[_thread# if > 1 thread/core] inside socket
AffMsk is AffinityMask(extended hex) for core and thread
CmbMsk is Combined AffinityMask(extended hex) for hw threads sharing cache
       CmbMsk will differ from AffMsk if > 1 hw_thread/cache
Extended Hex replaces trailing zeroes with 'z#'
       where # is number of zeroes (so '8z5' is '0x800000')
L1D is Level 1 Data cache, size(KBytes)= 32,  Cores/cache= 2, Caches/package= 4
L1I is Level 1 Instruction cache, size(KBytes)= 32,  Cores/cache= 2, Caches/package= 4
L2 is Level 2 Unified cache, size(KBytes)= 256,  Cores/cache= 2, Caches/package= 4
L3 is Level 3 Unified cache, size(KBytes)= 8192,  Cores/cache= 8, Caches/package= 1
      +-----------+-----------+-----------+-----------+
Cache |  L1D      |  L1D      |  L1D      |  L1D      |
Size  |  32K      |  32K      |  32K      |  32K      |
OScpu#|    0     8|    1     9|    2    10|    3    11|
Core  |c0_t0 c0_t1|c1_t0 c1_t1|c2_t0 c2_t1|c3_t0 c3_t1|
AffMsk|    1   100|    2   200|    4   400|    8   800|
CmbMsk|  101      |  202      |  404      |  808      |
      +-----------+-----------+-----------+-----------+

Cache |  L1I      |  L1I      |  L1I      |  L1I      |
Size  |  32K      |  32K      |  32K      |  32K      |
      +-----------+-----------+-----------+-----------+

Cache |   L2      |   L2      |   L2      |   L2      |
Size  | 256K      | 256K      | 256K      | 256K      |
      +-----------+-----------+-----------+-----------+

Cache |   L3                                          |
Size  |   8M                                          |
CmbMsk|  f0f                                          |
      +-----------------------------------------------+

Combined socket AffinityMask= 0xf0f

Package 1 Cache and Thread details

Box Description:
Cache  is cache level designator
Size   is cache size
OScpu# is cpu # as seen by OS
Core   is core#[_thread# if > 1 thread/core] inside socket
AffMsk is AffinityMask(extended hex) for core and thread
CmbMsk is Combined AffinityMask(extended hex) for hw threads sharing cache
       CmbMsk will differ from AffMsk if > 1 hw_thread/cache
Extended Hex replaces trailing zeroes with 'z#'
       where # is number of zeroes (so '8z5' is '0x800000')
      +-----------+-----------+-----------+-----------+
Cache |  L1D      |  L1D      |  L1D      |  L1D      |
Size  |  32K      |  32K      |  32K      |  32K      |
OScpu#|    4    12|    5    13|    6    14|    7    15|
Core  |c0_t0 c0_t1|c1_t0 c1_t1|c2_t0 c2_t1|c3_t0 c3_t1|
AffMsk|   10   1z3|   20   2z3|   40   4z3|   80   8z3|
CmbMsk| 1010      | 2020      | 4040      | 8080      |
      +-----------+-----------+-----------+-----------+

Cache |  L1I      |  L1I      |  L1I      |  L1I      |
Size  |  32K      |  32K      |  32K      |  32K      |
      +-----------+-----------+-----------+-----------+

Cache |   L2      |   L2      |   L2      |   L2      |
Size  | 256K      | 256K      | 256K      | 256K      |
      +-----------+-----------+-----------+-----------+

Cache |   L3                                          |
Size  |   8M                                          |
CmbMsk| f0f0                                          |
      +-----------------------------------------------+

Answer 2

它们假设要交错，以便连续的内核尽可能地分散负载。如果0和1在同一芯片上，那么仅使用两个内核的天真代码将浪费一半的缓存。

如此编号的核心应首先交替使用物理CPU。如果可能的话，他们应该下一个替代模具然后，他们应该通过单个芯片上的核心。如果可能的话，它们应该包括虚拟核心。

因此，如果您有两个物理CPU（P1，P2），每个双核（C1，C2）和每个超线程（V1，V2），核心应该： P1C1V1，P2C1V1，P1C2V1，P2C2V1，P1C1V2，P2C1V2，P1C2V2，P2C2V2

基本原理是允许不了解CPU拓扑的代码只获取尽可能多的内核，因为它知道如何使用并获得最佳性能。如果你只支持两个内核，你需要P1C1V1和P2C1V1，而不是P1C1V1和P1C1V2，否则你将大量浪费缓存和执行单元。

2芯片组Intel Westmere的CPU内核订购/编号

2 个答案: