Verilog编译错误（标识符未声明）

时间：2020-05-09 22:11:25

标签： verilog

我试图在下面的模块中弄清楚自己在做什么。任何帮助将不胜感激。

module controlCircuit(clk, op, start, reset, r1Hold, r2Hold, r1Load, r2Load, shift, c2, c1);

input [2:0] op;
input start, reset, clk;
reg [10:0] state;
output reg r1Hold, r2Hold, r1Load, r2Load, shift, c2, c1;
integer i, j, q;
integer stateIndex;

always @(posedge clk) begin
    if (reset) begin 
        state[0] = 1;
        for (i = 1; i<8; i = i+1) begin 
            state[i] = 0;
        end  
    end
    if (state[0]) begin 
        if(start) begin
            r1Load = 1;
            for (j = 0; j<7; j=j+1) begin 
                shift = 1;
                shift = 0;
            end
            state[0] = 0;
            state[1] = 1;
        end
    end
        else begin
            c2 = 0;
            c1 = 1;
            r1Hold = 1;
            r2Hold = 1;
        end
    end
    if (state[1]) begin 
        r1Hold = 1;
        r2Load = 1;
        c2 = 1;
        c1 = 0;
        for (q = 0; q<7; q=q+1) begin 
                shift = 1;
                shift = 0;
        end
        state[1] = 0;
        state[2] = 1;
        stateIndex = 2;
    end
    if (state[2]==1 || state[3]==1 || state[4]==1 || state[5]==1 || state[6]==1 || state[7]==1) begin 
        shift = 1;
        shift = 0;
        if (stateIndex == 7) begin 
            state[7] = 0;
            state[0] = 1;
        end
        else begin
            state[stateIndex] = 0;
            stateIndex = stateIndex + 1;
            state[stateIndex] = 1;
        end 
    end
 endmodule

这就是我得到的错误：

ERROR LOG 

og_a: Error 31004 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(115,6): Syntax error near `shift' found.
vlog_a: Note: Inside parser rule `generate_item'.
vlog_a: Error 31004 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(116,6): Syntax error near `shift' found.
vlog_a: Note: Inside parser rule `generate_item'.
vlog_a: Error 31004 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(118,11): Syntax error near `]' found.
vlog_a: Note: Inside parser rule `regular_range'.
vlog_a: Error 31004 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(119,11): Syntax error near `]' found.
vlog_a: Note: Inside parser rule `regular_range'.
vlog_a: Error 31004 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(120,4): Syntax error near `stateIndex' found.
vlog_a: Note: Inside parser rule `generate_item'.
vlog_a: Error 31004 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(123,4): Syntax error near `shift' found.
vlog_a: Note: Inside parser rule `generate_item'.
vlog_a: Error 31004 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(124,4): Syntax error near `shift' found.
vlog_a: Note: Inside parser rule `generate_item'.
vlog_a: Error 31004 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(126,12): Syntax error near `]' found.
vlog_a: Note: Inside parser rule `regular_range'.
vlog_a: Error 31004 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(127,12): Syntax error near `]' found.
vlog_a: Note: Inside parser rule `regular_range'.
vlog_a: Error 31004 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(130,21): Syntax error near `]' found.
vlog_a: Note: Inside parser rule `regular_range'.
vlog_a: Error 31004 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(131,5): Syntax error near `stateIndex' found.
vlog_a: Note: Inside parser rule `generate_item'.
vlog_a: Error 31004 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(132,21): Syntax error near `]' found.
vlog_a: Note: Inside parser rule `regular_range'.
vlog_a: Error 31006 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(109,7): Illegal reference in constant expression.
vlog_a: Error 31006 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(114,16): Illegal reference in constant expression.
vlog_a: Error 31006 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(114,23): Illegal reference in constant expression.
vlog_a: Error 31025 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(114,9): `q' is not a genvar or has already been used as an index variable in an outer generate loop.
vlog_a: Error 31007 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(118,4): Undeclared identifier `state'.
vlog_a: Error 31007 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(119,4): Undeclared identifier `state'.
vlog_a: Error 31006 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(122,7): Illegal reference in constant expression.
vlog_a: Error 31006 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(122,22): Illegal reference in constant expression.
vlog_a: Error 31006 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(122,37): Illegal reference in constant expression.
vlog_a: Error 31006 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(122,52): Illegal reference in constant expression.
vlog_a: Error 31006 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(122,67): Illegal reference in constant expression.
vlog_a: Error 31006 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(122,82): Illegal reference in constant expression.
vlog_a: Error 31006 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(125,8): Illegal reference in constant expression.
vlog_a: Error 31007 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(126,5): Undeclared identifier `state'.
vlog_a: Error 31007 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(127,5): Undeclared identifier `state'.
vlog_a: Error 31007 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(130,5): Undeclared identifier `state'.
vlog_a: Error 31007 C:\Users\zride\Documents\Syncad\Projects\ADS-Final\final.v(132,5): Undeclared identifier `state'.
vlog_a: Note: final_tb.v

1 个答案:

答案 0 :(得分：0)

您将end关键字之一放到了长always块中。我将您的缩进调整为更加一致，并添加了一些垂直空格以分隔不同的if/else块。这对我来说没有编译错误：

always @(posedge clk) begin
    if (reset) begin 
        state[0] = 1;
        for (i = 1; i<8; i = i+1) begin 
            state[i] = 0;
        end  
    end

    if (state[0]) begin 
        if(start) begin
            r1Load = 1;
            for (j = 0; j<7; j=j+1) begin 
                shift = 1;
                shift = 0;
            end
            state[0] = 0;
            state[1] = 1;
        end
    end else begin
            c2 = 0;
            c1 = 1;
            r1Hold = 1;
            r2Hold = 1;
    end

    if (state[1]) begin 
        r1Hold = 1;
        r2Load = 1;
        c2 = 1;
        c1 = 0;
        for (q = 0; q<7; q=q+1) begin 
                shift = 1;
                shift = 0;
        end
        state[1] = 0;
        state[2] = 1;
        stateIndex = 2;
    end

    if (state[2]==1 || state[3]==1 || state[4]==1 || state[5]==1 || state[6]==1 || state[7]==1) begin 
        shift = 1;
        shift = 0;
        if (stateIndex == 7) begin 
            state[7] = 0;
            state[0] = 1;
        end else begin
            state[stateIndex] = 0;
            stateIndex = stateIndex + 1;
            state[stateIndex] = 1;
        end 
    end
end

此外，您可能应该将阻塞分配更改为非阻塞，这对于顺序逻辑建议使用：

    state[0] <= 1;

等

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