Question

我已经用case语句和if语句尝试了这一点，但无法使其正常工作。我有下面的代码。它应该允许我选择一个ALU操作，然后设置结果的值。结果是一个信号，然后将其传递到输出（即输出节点）。

如您所见，我有实际的案例检查功能，可以做我想做的事情，还可以进行后备功能。我无法理解为什么它没有完成。但是，我的Output变量总是在测试台中返回未定义状态。当我在GTKWave中查看文件时，我可以看到“结果”值也保持未设置状态。但是，加法器恰好在做应做的事情，并输出正确的值。无论出于何种原因，case语句都拒绝设置它。

我还可以删除所有条件语句，只需将代码放入其中，一切就可以正常工作，但当然那是因为我有一个过于复杂的加法器而不是ALU。任何帮助将不胜感激。

entity ALU is
    port (
        A, B: in std_ulogic_vector(31 downto 0);
        Selection: in std_ulogic_vector(5 downto 0);
        Carry_in: in std_ulogic;
        Output: out std_ulogic_vector(31 downto 0);
        CF, ZF, NF, VF: out std_ulogic
    );
end ALU;

architecture ALU_ARCH of ALU is
component ADDER is
    port (
        A: in std_ulogic_vector(31 downto 0);
        B: in std_ulogic_vector(31 downto 0);
        Carry_in: in std_ulogic;
        Overflow: out std_ulogic;
        Carry_out: out std_ulogic;
        Sum: out std_ulogic_vector(31 downto 0)
    );
end component;

signal Adder_ci, Adder_co, Adder_overflow: std_ulogic;
signal Adder_B, Adder_sum: std_ulogic_vector(31 downto 0);

signal Results: std_ulogic_vector(31 downto 0);

begin
ADDITION: ADDER port map(A => A, B => Adder_B, Sum => Adder_sum, Carry_in => Adder_ci, Carry_out => Adder_co, Overflow => Adder_overflow);

process(A, B, Selection, Carry_In)
begin
case Selection is
    when "000000" =>  --ADD
        Adder_B <= B;
        Adder_ci <= '0';
        CF <= Adder_co;
        Results <= Adder_sum;       
        NF <= Results(31);
        VF <= Adder_overflow;
    when others =>
        Adder_B <= B;
        Adder_ci <= '0';
        CF <= Adder_co;
        Results <= Adder_sum;       
        NF <= Results(31);
        VF <= Adder_overflow;
end case;

end process;

Output <= Results; 

end ALU_ARCH;

我用来检查它的测试台列在下面的代码中，以防万一我在那做错了。

entity ALU_TB is
end ALU_TB;

architecture test_arch of ALU_TB is
    component ALU
    port (
        A, B: in std_ulogic_vector(31 downto 0);
        Selection: in std_ulogic_vector(5 downto 0);
        Carry_in: in std_ulogic;
        Output: out std_ulogic_vector(31 downto 0);
        CF, ZF, NF, VF: out std_ulogic
    );
    end component;

signal Carry_in, CF, ZF, NF, VF: std_ulogic;
signal Selection: std_ulogic_vector(5 downto 0);
signal A, B, Output: std_ulogic_vector(31 downto 0);

begin
    ALUb: ALU port map(A => A, B => B, Selection => Selection, Carry_in => Carry_in, Output => Output, CF => CF, NF => NF, ZF => ZF, VF => VF);

    process 

    variable AT : integer;  
    variable BT : integer;  
    begin
        Selection <= "000000";
        AT := 80;
        BT := 16;
        Carry_in <= '0';
        A <= std_ulogic_vector( to_signed(AT, A'length) ); 
        B <= std_ulogic_vector( to_signed(BT, B'length) ); 
        wait for 1 ns;
        if Output /= std_ulogic_vector( to_signed( (AT + BT) , Output'length) ) then 
            assert false report "Failed in 1";
        end if;

        wait;

    end process;

end test_arch;

我不确定这是否重要，但是我正在Mac上的GHDL中完成所有这些操作。

Answer 1

当您的测试设置了输入时，触发选择过程以执行其分配，从而导致新的加法器输出。但是，Adder_sum中的更改不会触发该过程，因为它不在灵敏度列表中，因此该和不会分配给Results信号。

有几种解决方案。一种是使用process（all）触发所有信号。

VHDL条件句不会设置值

1 个答案: