我一直在尝试模拟我的代码（合成过程中没有错误，也没有实现步骤，并且还满足了时序约束），但是输出显示为“ X”，并且在读取所有输入之前该过程已经结束。我不知道为什么？！ 这是我用于计算相关性的代码：
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity corr_1 is
generic( N : integer := 4; -- N is the width of each input symbpl of the signals
M : integer := 4); -- M is the length of chosen part of the signals to be correlated(indicating iteration)
port( clk : in std_logic;
xr,xi : in std_logic_vector( N-1 downto 0); -- real and imaginary N_bit symbol of the first signal
yr,yi : in std_logic_vector( N-1 downto 0); -- real and imaginary N_bit symbol of the second signal
rr_0 : out std_logic_vector(N+N+2 downto 0); -- real part of the output correlation with lag=0
ri_0 : out std_logic_vector(N+N+2 downto 0); -- imaginary part of the output correlation with lag=0
rr_1 : out std_logic_vector(N+N+2 downto 0); -- real part of the output correlation with lag=1
ri_1 : out std_logic_vector(N+N+2 downto 0) -- imaginary part of the output correlation with lag=1
);
end corr_1;
architecture hard_arch of corr_1 is
signal Nyi,Cyi : std_logic_vector(N-1 downto 0); --signals used to conjugate the second signal
signal yi_c : signed(N-1 downto 0); --signals used to conjugate the second signal
signal yr_d,yi_d : std_logic_vector(N-1 downto 0); --delayed signals used to do correlation with lag=1
signal temr_0,temi_0,temr_1,temi_1 : std_logic_vector(N+N downto 0); --midterm signals for accumulator
signal Srr_0,Srr_1,Sri_0,Sri_1 : signed(N+N+2 downto 0) :=(others=>'0');--midterm signals for accumulator
signal counter_0 : integer range 0 to M; --counter with initial value of 0
signal counter_1 : integer range 0 to M; --counter with initial value of 0
-- component declaration (as we are using complex multiplier)
component cmux_m1
port (ar,ai : in std_logic_vector( N-1 downto 0);
br,bi : in std_logic_vector( N-1 downto 0);
pr,pi : out std_logic_vector( N+N downto 0)
);
end component;
begin
-- conjugating process using two's complement for the imaginary part of the second input signal
process(clk)
begin
Nyi<= not yi;
yi_c<=signed(Nyi);
if rising_edge(clk) then
Cyi<=std_logic_vector(yi_c + 1); --now conjugated signal is ready to be used
end if;
end process;
-- delaying our second signal to prepare for correlation with lag=1
process(clk)
begin
if rising_edge(clk) then
yr_d<=yr;
yi_d<=Cyi;
end if;
end process;
-- calculating correlation with lag=0
cmult_unit_0 : cmux_m1
port map(ar=>xr, ai=>xi, br=>yr, bi=>Cyi, pr=>temr_0, pi=>temi_0);
process(clk,xr,yr)
begin
if counter_0 < M then
if rising_edge(clk) then
Srr_0<= signed(temr_0) + Srr_0;
Sri_0<= signed(temi_0) + Sri_0;
rr_0<=std_logic_vector(Srr_0);
ri_0<=std_logic_vector(Sri_0);
counter_0<=counter_0 + 1;
end if;
elsif counter_0=M then
Srr_0<=(others=>'0');
Sri_0<=(others=>'0');
rr_0<=(others=>'0');
ri_0<=(others=>'0');
end if;
end process;
-- calculating correlation with lag=1
cmult_unit_1 : cmux_m1
port map(ar=>xr, ai=>xi, br=>yr_d, bi=>yi_d, pr=>temr_1, pi=>temi_1);
process(clk,xr,yr)
begin
if counter_1 < M then
if rising_edge(clk) then
Srr_1<= signed(temr_1) + Srr_1;
Sri_1<= signed(temi_1) + Sri_1;
rr_1<= std_logic_vector(Srr_1);
ri_1<= std_logic_vector(Sri_1);
counter_1<= counter_1 + 1;
end if;
elsif counter_1=M then
Srr_1<=(others=>'0');
Sri_1<=(others=>'0');
rr_1<=(others=>'0');
ri_1<=(others=>'0');
end if;
end process;
end hard_arch;
在模拟中，当四个上升沿（计数器等于M）之后，输出被设置为零，但在此之前的那个时期它不起作用。