在体系结构中，我不知道该摩尔机器的类型和信号代码行是否正确，有人可以指出错误吗？

Question

我是QuartusII9.1的新手，不了解逻辑类型与下面各行中的错误之间的关系。摩尔机器的状态A，B，C具有两个输入X1，X0。此外，我在此过程中使用了一个SignalX。任何建议都会有所帮助！

Library Ieee;
Use Ieee.std_logic_1164.All;

Entity Sm_VHDL Is
    Port
    (
    X,RESETN,CLOCK: In std_logic;
    Z             : Out std_logic);
    End Sm_VHDL;
ARCHITECTURE behavior Of Sm_VHDL Is
    Type std_logic Is (A,B,C);
    Signal Q: std_logic;
    Begin
    Z<='1' When Q=C Else '0';
    Process(CLOCK,RESETN)
      Begin
      If RESETN='0' Then 
        Q<=A;
      Elsif CLOCK'Event And CLOCK='1' Then
        Case Q Is
        when A=>
            Case X Is
            when "00"=>
            Q<=A;
            when "01"=>
            Q<=C;
            when "10"=>
            Q<=B;
            when "11"=>
            Q<=A;
            End Case;
        when B=>
            Case X Is
            when "00"=>
            Q<=A;
            when "01"=>
            Q<=C;
            when "10"=>
            Q<=B;
            when "11"=>
            Q<=B;
            End Case;
        when C=>
            Case X Is
            when "00"=>
            Q<=C;
            when "01"=>
            Q<=C;
            when "10"=>
            Q<=B;
            when "11"=>
            Q<=A;
            End Case;
        End Case;
      End If;
    End Process;
End behavior;

  

错误（10515）：Sm_VHDL.vhd（23）处的VHDL类型不匹配错误：std_logic   类型与字符串文字不匹配。

第25,27和27行的错误相同。