在Chisel的象素中打印似乎输出了寄存器值的更新版本,这使得相同的Chisel打印代码在Chisel后端和验证程序后端中的行为有所不同。
在使用Chisel后端时,打印似乎只是记录硬件对象的参考,但是在当前步骤的逻辑模拟之后执行打印,然后参考会以更新的值进行回复。
我搜索了凿子仓库的问题和凿子用户组,但很少有关于此主题的讨论。
这是chisel-template回购中自成一体的代码示例。
package myrtl
import chisel3._
import chisel3.iotesters._
class Foo extends Module {
val io = IO(new Bundle {
val in = Input(UInt(32.W))
val out = Output(UInt(32.W))
})
val v = Wire(UInt(32.W))
when (v === 0.U) {
printf(p"v $v\n")
}
val reg = RegInit(0.U(32.W))
reg := io.in
io.out := reg
v := reg
}
class FooTester(dut: Foo) extends PeekPokeTester(dut) {
poke(dut.io.in, 32)
step(1)
}
object TestMain extends App {
iotesters.Driver.execute(args, () => new Foo)(dut => new FooTester(dut))
}
请注意printf
的条件。荒谬的是,v === 0.U
启用了打印,但是将此v
输出为32
的值。
答案 0 :(得分:2)
我相信这是一个已报告的错误,其中printf
语句的依赖关系未正确计算(并已得到修复)。
在过去的一年中,有许多重构可能是解决这个问题的原因:
您可以尝试在声呐类型上切换到1.3-SNAPSHOT
并重新测试吗?
diff --git a/build.sbt b/build.sbt
index 6d18fe7..c13d44d 100644
--- a/build.sbt
+++ b/build.sbt
@@ -41,11 +41,10 @@ resolvers ++= Seq(
// Provide a managed dependency on X if -DXVersion="" is supplied on the command line.
val defaultVersions = Map(
- "chisel3" -> "3.1.+",
- "chisel-iotesters" -> "[1.2.5,1.3.0["
+ "chisel-iotesters" -> "1.3-SNAPSHOT"
)
-libraryDependencies ++= Seq("chisel3","chisel-iotesters").map {
+libraryDependencies ++= Seq("chisel-iotesters").map {
dep: String => "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep)) }
scalacOptions ++= scalacOptionsVersion(scalaVersion.value)
通过对build.sbt
的这些修改,我可以看到不打印任何内容的预期行为。这与Verilator有所不同,Verilator在模拟开始之前似乎只有一张印刷品。使用1.3-SNAPSHOT
:
sbt:chisel-module-template> test:runMain myrtl.TestMain --backend-name treadle
[warn] Multiple main classes detected. Run 'show discoveredMainClasses' to see the list
[info] Running myrtl.TestMain --backend-name treadle
[info] [0.001] Elaborating design...
[info] [0.108] Done elaborating.
Total FIRRTL Compile Time: 408.8 ms
file loaded in 0.071117471 seconds, 15 symbols, 12 statements
[info] [0.001] SEED 1568033935603
test Foo Success: 0 tests passed in 6 cycles in 0.012474 seconds 481.00 Hz
[info] [0.003] RAN 1 CYCLES PASSED
[success] Total time: 2 s, completed Sep 9, 2019 8:58:56 AM
并且在使用verilator时(带有一些输出片段):
sbt:chisel-module-template> test:runMain myrtl.TestMain --backend-name verilator
[warn] Multiple main classes detected. Run 'show discoveredMainClasses' to see the list
[info] Running myrtl.TestMain --backend-name verilator
[info] [0.001] Elaborating design...
[info] [0.108] Done elaborating.
Total FIRRTL Compile Time: 440.6 ms
[info] [0.001] SEED 1568034082729
[info] [0.007] v 0
[info] [0.007] 0
Enabling waves..
Exit Code: 0
[info] [0.011] RAN 1 CYCLES PASSED
[success] Total time: 4 s, completed Sep 9, 2019 9:01:25 AM