Question

在Verilog和c语言中，我可以通过使用代字号（tilde）运算符来轻松取反向量。示例：

// Verilog
module try;
wire [7:0] a = 8'b1111_0000;
reg  [7:0] b;

initial begin
    b = ~a;
    // b = 8'b0000_1111;
end

endmodule

在VHDL中我该怎么做？

-- VHDL
library ieee;
use ieee.std_logic_1164.all;

entity design is
end entity;

architecture rtl of design is
    a: std_logic_vector(7 downto 0) := X"0F";
    b: std_logic_vector(7 downto 0);
begin
    b <= ?negate? a;
    -- result: b = X"F0"
end architecture;

Answer 1

not运算符：

b <= not a;

Answer 2

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end entity;

architecture rtl of testbench is
begin

process
    variable a :std_logic_vector(7 downto 0) := X"F0";
    variable b :std_logic_vector(7 downto 0);
begin
    b := not a;
    report "a:" & to_hstring(a);
    report "b:" & to_hstring(b);
    wait;
end process;
end architecture;

C:\> ghdl.exe -a --std=08 --ieee=synopsys --work=work ./testit.vhd
C:\> ghdl.exe --elab-run --std=08 testbench --ieee-asserts=disable
./testit.vhd:17:5:@0ms:(report note): a:F0
./testit.vhd:18:5:@0ms:(report note): b:0F

VHDL中的Verilog波浪号运算符“〜”等效吗？

2 个答案: